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Chia-Chou Chuang

dblp:349/9401 · DBLP profile ↗
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3ranked-venue papers
1as first author
3since 2021 · last 2026
0009-0008-4424-1304ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 77% Integrated circuit design · 23%
Network and information security
1 paper
Cryptographic primitives and cryptanalysis · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
error detection
1.012026
CRC-Based Error Detection Mechanism for Multiplicative Inverse in Redundant Basis S -Box · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Cryptographic primitives and cryptanalysis › cryptographic implementation
s-box implementation
0.312026
CRC-Based Error Detection Mechanism for Multiplicative Inverse in Redundant Basis S -Box · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026

Methods — techniques the papers use, named apart from their topics

cyclic redundancy check · 2.0
YearPublicationVenuePosition
2026 High-Performance AES-GCM Hardware via Circuit and Architecture Co-Design of AES and GHASH
Chia-Chou Chuang, Chuan-Kai Su, Ying-Sheng Huang, Da-Huei Lee, Pei-Yin Chen
ISCAS1
2026 CRC-Based Error Detection Mechanism for Multiplicative Inverse in Redundant Basis S -Box
Ying-Sheng Huang, Chia-Chou Chuang, Chien-Chung Ho, Pei-Yin Chen
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2025 Live Demonstration: SoC Design of Lightweight Cryptography for Real-Time Monitoring System
abstract
This live demonstration shows a low-cost but high-performance hardware IP for video stream encryption and authentication on real-time monitoring system. The proposed IP is essentially based on the established standard of lightweight cryptography (LWC) by NIST in 2023, which is called Ascon cipher. For maintaining the frame rate of the video, a high-speed and low-cost hardware IP is proposed with a step-by-step setup procedure introduced in this brief. Given that the recursive permutation of Ascon algorithm, the cost of the proposed Ascon cipher IP can be sustainably reduced by round-based design. The video stream encryption system is realized on Xilinx PYNQ-Z2 board with some peripheral IPs embedded in that FPGA board. Implementation results show the designed IP and the SoC system can perform better than the previous work.
Yi-Hsuan Lee, Po-Chun Chen, Yu-Cheng Huang, Chia-Chou Chuang, Narn-Yih Lee, Pei-Yin Chen
ISCAS4