This paper presents an analytical study and modeling of the Helical ladder switched capacitor converters (HLSC). The higher output impedance (ROUT) problem in the conventional ladder switched capacitor converter (CLSC) is addressed in the HLSC by identifying the large charge carrying flying capacitors of CLSC and reconfiguring them to reduce the charge flow. A systematic process is proposed to develop an HLSC architecture for any given voltage conversion ratios (VCR) using its equivalent CLSC architecture. As the switched capacitor converter (SCC) performance mainly depends on the ROUT, analytical models are developed to calculate the ROUTusing switching frequency (fSW), total flying capacitance (Ctot), and load current (IL) for an n-stage HLSC and CLSC. From these models, the variation of charge sharing loss and parasitic capacitance loss, and their impact on the efficiency (η) and output voltage (VOUT) is analyzed across all the VCRs. The comparison between CLSC and HLSC results shows that the HLSC has superior performance over CLSC. The developed models are useful for comparing the different performance metrics of various SCC topologies.

This paper presents a sub$-V_{\text{TH}}$ring oscillator (RO) based digital temperature sensor where the ROs are designed using the sub$-V_{\text{TH}}$transmission gates (TG). Two ROs are designed with different TGs to generate$f_{\mathrm{H}}$and$f_{\mathrm{L}}$frequencies, whose frequency ratio$(f_{\mathrm{H}}/f_{\mathrm{L}})$increases linearly with temperature. The temperature-dependent$f_{\mathrm{H}}/f_{\mathrm{L}}$ratio is converted to digital code (TCODE) using two asynchronous counters. Further, a cascoded 3T regulator is proposed to power the sensor and reduce its line sensitivity. The sensor prototype is designed in 180 nm while operated at 0.7 V supply it consumes 7.7 nW of power (3.6 nW by core and 4.1 nW by digital block) with$-1.5^{\circ}\mathrm{C}/+1.94^{\circ}\mathrm{C}$inaccuracy across 0°C to 100°C range after 2-point calibration at 10°C and 80°C. It achieves an 0.15°C resolution and FoM of 19 pJ-K2with 1.28 ° C/V line sensitivity when operated from 0.7 V to 2.2 V supply voltage.

This paper presents a current reference using temperature-compensated CMOS resistors. In the proposed circuit, the constant current is generated by compensating complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) CMOS resistors. The CMOS CTAT resistor is designed using a MOS biased in the deep-triode region. In contrast, the PTAT resistor is derived using the MOS biased in the sub-threshold triode region with a$\boldsymbol{V}_{\mathbf{TH}}-\mathbf{tracking}$voltage. The reference current is generated using a 3T regulator and the temperature-compensated CMOS resistors. The sensor prototype is designed in 180 nm for 172 pA of reference current$(\boldsymbol{I}_{\mathbf{REF}})$at a temperature coefficient (TC) of 327 ppm/ ° C from 0 ° C to 80 ° C. It has 0.63 nW power consumption at 1.1 V supply with an average line sensitivity of 0.63 %/V when operated from 1.1 V to 2.1 V supply voltage.

We present an ultra-low-power band-gap reference-based regulator and a unique method of generating a proportional-to-absolute-temperature (PTAT) voltage and a PTAT current. The PTAT current is used to generate a BJT complementary-to-absolute-temperature (CTAT) voltage. This CTAT voltage and PTAT voltage are added to generate a regulated output voltage in the negative feedback loop to drive the load. The output of the proposed regulator is temperature stable from −20° C to 85° C with a mean variation of less than 20 ppm/° C. The proposed technique eliminates the need for an additional start-up circuitry, which is mandatory for conventional architectures. The 1.18 V output voltage regulator, designed in a 180-nm CMOS process, has a simulated line regulation of 0.1 %/V with a power consumption of 15 nW at room temperature. The proposed regulator can drive the load from 0 to 30 mA.

Conventional modeling and simulation of$n$-output dc–dc converters requires$(n+1) \times (n+1)$matrix computations. This approach increases the modeling approach’s complexity and increases the design and simulation time required for the modeling process. A state separate modeling methodology is proposed where each state of the dc–dc converter is considered separately and combined with the help of a multiplexer. The proposed modeling approach is modular and thus improves the scalability to multiple outputs. The proposed methodology aids the designer in designing and modeling multioutput dc–dc converters faster, enabling fast prototyping. The proposed model outperforms the existing mathematical models in terms of computation time. The output voltage variation to duty cycles has a root mean square error in between 0.08 and 0.22 V.

This paper presents a hybrid multiphase interleaving technique for bottom plate parasitic charge sharing and ripple reduction in SC converter (SCC). The proposed technique uses multiphase interleaving for reducing ripple and scalable parasitic charge redistribution technique for reducing bottom plate parasitic loss, and incorporates them to achieve both features. An 8-core, 8-phase interleaved 1/2 SCC with 3 charge redistribution steps is derived using the proposed technique and implemented in the 180 nm CMOS process. Post-layout simulations of 8C8P validate that the proposed hybrid technique achieves 83% efficiency and 50% lesser ripple than the existing SPCR technique with the same flying capacitance and switch conductance.

A 0.13 nW ultra-low-power over-temperature-protection circuit is proposed for highly integrated System-on-Chips (SoC). The circuit detects a temperature of $120^{\circ} \text{C}$ but can be programmed for other temperature thresholds. The temperature detection is achieved by comparing a reference voltage with a 2-transistor ultra-low-power inverter architecture. The 2transistor inverter is designed to have a proportional-to-absolute-temperature (PTAT) threshold characteristic, and the reference voltage is generated on-chip with a 2-transistor reference. The design is implemented in $0.18 \mu \text{m}$ CMOS technology and occupies an area of $0.0117 \text{mm}^{2}$. The design operates from 0.5 V supply voltage and has a line sensitivity of $0.1^{\circ} \text{C}/\text{V}$ and a hysteresis width of $7.7^{\circ} \text{C}$, as seen from simulations. The trim-free design has a worst-case process variation of 4%.

The importance of area optimizations leads to the removal of balun between LNA and mixer in RF receivers and this, in turn, lead to the use of single-ended passive mixers in the place of its differential counterparts. But the single-ended topology resulted in the variation of IIP2 performance of mixers across temperature and process corners as well as across different frequencies of operation compared to its differential counterpart. The IIP2 of RF receivers showed peak performance at different mixer bias voltages at different corners and bands. In this paper, we propose a threshold voltage tracking circuit in 14-nm FinFET technology to bias the passive direct-conversion single-ended mixers such that it enhances the IIP2 performance of mixers up to 20dB across temperature and process corners. This design includes a temperature-dependent bias voltage generation circuit with different slopes over temperature which can be varied with a step size of nearly 8mV and an additional DC voltage calibration circuit to generate differential bias voltages independently in I and Q channels. The temperature slope of the bias voltage being generated is dependent on the NMOS width and the current flowing through the NMOS. This enables us to generate the mixer bias voltages with different slopes over temperature and allows us to employ the same circuit to bias the mixer at different frequencies of operation, temperature and process corners.

A picowatt programmable CMOS-based voltage reference (VR) for wireless sensor nodes (WSNs) is proposed in this work. It uses a pMOS current source and an nMOS current sink to generate a temperature-independent output voltage. A body bias potential is used to control the threshold voltage of the nMOS current sink to generate programmable output voltage. The architecture can achieve temperature compensated reference voltages for different temperature characteristics of body bias with the help of digital trimming. The body bias is generated on-chip using a dedicated body bias generation block. The prototype circuit is fabricated in the 0.18-$\mu \text{m}$CMOS process with deep-n-well (DNW) and occupies a total area of 0.022 mm2including the body bias block and a 10-pF decoupling MIM capacitor. The circuit provides output voltages from 250 to 370 mV. A total of ten chips from two different wafers (five chips per wafer) were measured. The average temperature coefficient (TC) is measured to be 72.17 ppm/$^\circ \text{C}$over$- 40\,\,^\circ \text{C}$to 80$^\circ \text{C}$for a reference voltage of 349.7 mV. The average line sensitivity (LS) obtained is 0.093%/V with a power supply rejection (PSR) of −39 dB at 100 Hz.

A 192 pA current reference is proposed for ultra-low-power applications. The sub-threshold design based circuit employs three-transistor-regulators to provide a CTAT (complimentary-to-absolute-temperature) source to gate voltage, to a PMOS device that minimizes the temperature variation of the reference current. Consistent performance across process variations is achieved through digital trimming and body bias control. A temperature coefficient (TC) of 542 ppm/ °C is attained at nominal process with a minimum and maximum TC of 350 ppm/ °C and 729 ppm/ °C, respectively, across all process corners. The circuit operates at a worst case minimum supply voltage of 700 mV and the power consumption is 1.06 nW at the nominal process and temperature. The same architecture is reused for a reference current of 87.7 nA, which improves the TC to 91.2 ppm/ °C. The circuit is designed in standard 0.18 μm CMOS technology.

We present an ultra-low-power fractional bandgap-based voltage reference and a unique method of generating a small proportional-to-absolute-temperature (PTAT) current. The PTAT current is used to generate a BJT complementary-to-absolute-temperature (CTAT) voltage. We have achieved temperature compensation of the generated reference voltage by subtracting a sub-threshold MOS CTAT voltage from the BJT CTAT voltage. The difference between the two CTAT voltages is temperature stable from -50°C to 85°C with a mean variation of less than 95 ppm/°C measured across chips, without any additional trim. The proposed technique eliminates the need for additional start-up circuitry, which is mandatory for conventional architectures. The 260-mV voltage reference designed in a 180-nm CMOS process has a measured line regulation of 0.23 %/V and consumes 1 nW at room temperature.

In this paper, a burst mode constant ON-time-controlled, energy harvesting charger is presented. The proposed boost converter system uses the burst mode control to improve the efficiency by 11%, compared to the conventional single-mode energy transfer implementation with an ultralow-power input comparator. A technique to deduce an optimum inductor energizes time across the given input range, for which the maximum converter efficiency is demonstrated. An internally triggered, capacitor-less sample-and-hold block addresses the leakage issue in the conventional fractional open-circuit voltage maximum power point tracking systems. The system is capable of charging a super-capacitor of 4.7 mF, from 1.8 to 3.3 V from an input power of 50 μW to 100 mW by maintaining the maximum power at the input. The entire system is designed and fabricated in the standard 180-nm CMOS technology, and the measurement results show a peak efficiency of 92% at 98-mW input power for the output voltage of 3 V and efficiency ≥65% across the range of input voltages more than 0.3 V for the output voltage of 1.8 V.

A temperature compensated under voltage lockout (UVLO) circuit for ultra-low power applications is presented. The UVLO operation is achieved using two transistors with different threshold voltages and a source follower. The difference in the thresholds of the two transistors is used to create a reference voltage. As the supply voltage rises, the generated reference voltage tracks the supply till its designed voltage value and thereafter becomes a constant. This reference voltage is applied to a self-referenced common-source stage and is further amplified by CMOS inverters to arrive at a decision to lock out the supply or not. The designed UVLO consumes 200 pA of current at 1.8 V supply. The measured low-to-high trip points (LHTP) and high-to-low trip points (HLTP) are 1.28 V and 1.12 V with a variability of 208 ppm/°C and 200 ppm/°C respectively. These trip points are programmable from 1.1 V to 1.4 V in steps of 100 mV. The design occupies 0.00723 mm2in standard 180 nm CMOS.

An Event Triggerred - Fractional Open Circuit Voltage Maximum Power Point Tracking (ET-FOCV MPPT) technique is introduced for irradiance change aware open-circuiting in FOCV systems. The ET-FOCV scheme is implemented using a novel Irradiance Change Detection (ICD) block which is based on gradient based current sensing technique. By avoiding the periodic open circuiting in the absence of irradiance change, this technique extracts more energy than the conventional FOCV systems. The proposed ICD block can operate from 10 Hz to 100 kHz system clock frequencies targeting micro scale energy harvesting systems. With the ICD block and ET-FOCV technique, the proposed solar energy harvesting system harvests energy from input power level of 200 μW to 20 mW and input voltage level of 100 mV to 1.5 V and charges a battery to 3.3 V by boost operation. The entire system is implemented in standard 180 nm CMOS technology and the extracted results validate the system performance.

In this paper, a burst mode constant ON-time-controlled, energy harvesting charger is presented. The proposed boost converter system uses the burst mode control to improve the efficiency by 11%, compared to the conventional single-mode energy transfer implementation with an ultralow-power input comparator. A technique to deduce an optimum inductor energizes time across the given input range, for which the maximum converter efficiency is demonstrated. An internally triggered, capacitor-less sample-and-hold block addresses the leakage issue in the conventional fractional open-circuit voltage maximum power point tracking systems. The system is capable of charging a super-capacitor of 4.7 mF, from 1.8 to 3.3 V from an input power of 50 μW to 100 mW by maintaining the maximum power at the input. The entire system is designed and fabricated in the standard 180-nm CMOS technology, and the measurement results show a peak efficiency of 92% at 98-mW input power for the output voltage of 3 V and efficiency ≥65% across the range of input voltages more than 0.3 V for the output voltage of 1.8 V.

A human body heat driven thermal energy harvesting regulator with high output power at low input voltages and small form factor, suitable to power compact and feature-packed wearable biomedical Internet of Things (IoT) nodes, is developed in this paper. The system demonstrates$2.3{\times }$higher throughput than prior art at low input voltages with a maximum conversion ratio of$83 \times $, in order to support complex and power hungry IoT operations like onboard processing and data transmission. The peak load supportable by the system is extended by utilizing maximum power extraction and minimizing converter losses in a single-stage compact power management unit. A fixed-frequency technique, independent of input voltage variation is proposed to maximize output power when load demands. A digital switch controller with ultra low power digitally controllable delay circuit is implemented to perform zero current switching to improve efficiency. The system, fabricated in 180-nm standard CMOS process, operates from open circuit input voltages ranging from 25 to 210 mV while supplying a regulated 1 V output. The functionality of the system is demonstrated in real-time by integrating the regulator with an emulated cardiac monitoring IoT node. The system delivers a peak power of 1.03 mW at open circuit voltage of the transducer,${V} _{\text {TEG}}$, of 210 mV, generated at body to ambient temperature difference of ~8 °C. The total area occupied by the system is 0.13 mm2and has an end-to-end peak efficiency of 65% at${V} _{\text {TEG}}$of 50 mV in measurement.