This paper presents the first reported measurements of impedance plethysmography (IPG) signals directly from the human fingertip for the purpose of evaluating peripheral hemodynamics. The human fingertip serves as a vital non-invasive access point for cardiovascular monitoring, with photoplethysmography (PPG) widely adopted for its assessment of superficial blood flow. However, the optical sensing depth of PPG limits its capability to fully characterize deeper peripheral hemodynamics. Here, we developed a novel four-electrode fingertip IPG prototype and measurement protocol, enabling the consistent capture of pulsatile impedance waveforms reflecting blood volume changes within the digit. Preliminary data from two participants illustrates clear signal reproducibility and enables the derivation of key pulse wave metrics, including pulse arrival time (PAT). Given IPG's electrical sensing principle, distinct from PPG's optical approach, our findings suggest that fingertip IPG offers a complementary “new window” into peripheral circulation. This work establishes fingertip IPG as a significant advancement for non-invasive physiological monitoring, holding promise for both clinical applications and wearable health sensing.

This paper explores the use of discrete optimization techniques for variability-aware analog circuit synthesis, with an observation that the continuous design space can be effectively covered by a finite number of discrete points when parameter variation is present. Three algorithms are described that can leverage a discretized design space yet mitigate its dimensionality scaling problem: an isotropic discretization scheme, which can fill the neighborhood of any given point with only quadratically-increasing number of nearest neighbors placed at equal distances as the space dimension increases, a stochastic hill-climbing algorithm, which evaluates only a partial set of nearest neighbors yet finds the local optimum at the reduced cost, and an incremental Monte Carlo sampling algorithm, which draws the minimal number of Monte Carlo samples just enough to determine the superior design point during the local search process. These algorithms help in finding the optimal design of analog circuits efficiently. For instance, for a digitally-controlled oscillator example, its discretized design space consists of 5 565 907 points but the optimal point was found by evaluating only 40 design points and running only 21 Monte Carlo simulations per point in average (824 in total).

This paper presents an efficient method for extracting a yield-aware Pareto front between two competing metrics of an analog circuit block, with the purpose of performing hierarchical, system-level optimization using the component-level Pareto fronts as meta-models. The proposed method consists of three steps: finding a set of Pareto-optimal design points by tracing them on a discrete grid, estimating the yield distribution of each optimal design point using a control-variate technique, and constructing a yield-aware Pareto front by interpolation. The proposed algorithm is demonstrated on a problem of finding the optimal power allocation among the components composing a clock recovery path to minimize the final clock jitter. The algorithm can estimate the Pareto front of each circuit block within a 2% error, expressing the minimum achievable jitter with 99% yield for different power budgets, while requiring only 600 ~ 1100 Monte-Carlo simulation samples in total.

This paper proposes the use of discrete optimization techniques for variability-aware analog circuit synthesis. Starting from an observation that the continuous design space of analog circuits can be effectively covered by a finite number of discrete points in presence of variations, new algorithms are explored to address three aspects of discrete optimization: discretizing a continuous design space, selecting candidate points on the discretized grid, and comparing the statistical measures between multiple candidate points. A digitally-controlled oscillator (DCO) example demonstrates that the proposed optimization technique can efficiently find the design that balances between the resolution, linearity, phase noise, and power dissipation.