This paper presents a neuromorphic CMOS Delta-Sigma modulator for the robust and energy-efficient readout of amperometric electrochemical sensors. The circuit makes use of an adaptive integrate-and-fire scheme to deliver asynchronous A/D conversion and attenuation of background currents with minimal power requirements. The modulator reuses the dynamic characteristics of the electrode-electrolyte interface for quantization noise shaping, and it offers potentiostatic control of the voltage difference between working and reference electrodes of a three-electrode electrochemical cell. Electrical simulation results are reported at transistor level for a smart electrochemical sensor currently being integrated in a 1.2-V 65-nm 9-metal CMOS technology. The frontend exhibits a tunable off-band rejection of 20 dB with a peak SNR of 61dB and$70-\mu\mathrm{W}$power consumption.

This paper presents a 0.8-mW 0.2-mm29-level second-order single-loop SC Delta-Sigma modulator (ΔM) ADC in 1.8-V 0.18-μm CMOS technology for low-power high-resolution sensing applications. The ΔM circuit features 94.6-dB peak SNDR in 50-kHz bandwidth and 103.5 dB SFDR up to -1 dBFSinput for 2-Vpp differential full scale. The proposed built-in CDS flicker noise cancellation allows a net improvement of 10 dB FOMS. The bootstrapping-free CMOS circuits incorporate variable-mirror Class-AB switched OpAmps and a 10μW resistor-less flash quantizer. The obtained 172.6-dB FOMSis competitive within the state-of-art high-resolution (SNDR > 90 dB) and generalpurpose (bandwidth > 20 kHz) SC ASM ADCs.

This paper presents a potentiostatic-amperometric Delta-Sigma modulator (ΔΣM) for electrochemical sensors, which reuses the electrode-electrolyte impedance for quantization noise shaping. The proposed ΔΣM is based on a second-order single-bit CT architecture and it includes a cancellation mechanism of the flicker noise coming from the feedback DAC. Rail-to-rail CMOS basic building blocks for the ΔΣM circuit implementation are presented with the aim of allowing a wide-range potentiostatic operation. Post-layout simulation results are reported for a complete 72-μW 90-dB smart electrochemical sensor frontend currently being integrated in 0.18-μm 6-metal CMOS technology.

This paper presents a novel frequency-domain multiplexing scheme of liquid-gate GFET sensors for large-scale μECoG recording. The proposed technique allows the hybrid integration of GFET arrays and read-out ICs. In order to avoid artifacts, the proposal does not employ any switch in the GFET array and it is insensitive to the flicker noise of the CMOS frontend. A modular read-out IC architecture targeting the continuous acquisition of up to 1024 μECoG channels is introduced together with a collection of low-power CMOS circuits for the practical implementation of each building block. A test chip of the proposed system is currently being integrated in 0.18-μm 6-metal CMOS technology.

This paper proposes a compact switched-capacitor (SC) multi-bit flash quantizer for low-power high-resolution delta-sigma modulators (ΔΣMs). First, a general power model for single-loop ΔΣMs is presented to show the importance of using multi-bit quantization when facing high-resolution specifications. In this context, a SC multi-bit quantizer circuit is proposed, which exhibits low-power operation, high modularity, single comparator design and compatibility with both multi-feedforward ΔΣM architectures and other SC low-power circuit techniques, like clocked comparators and switched OpAmps. A practical 50-kHz 16-bit ΔΣM design case is also presented.

This paper presents a 128 × 128-pix high-speed PbSe-CMOS uncooled MWIR imager with pixel digital output. The proposed in-pixel A/D converter based on integrate-and-fire modulation achieves good linearity even at 20 Meps thanks to its soft-reset mechanism. Class-AB CMOS circuits are proposed to keep static power consumption below 10 μW/pix. Each DPS cell also includes its own analog reference and bias generator. The resulting pixel digital-only I/O interface ensures low crosstalk at the FPA level. From post-layout simulation results, the imager is capable of delivering 14 bit up to 1 kfps or alternatively 4 kfps up to 10 bit. The presented MWIR imager is currently being integrated in the 0.18-μm 1P6M CMOS technology from X-FAB.

This paper presents a complete family of integrate- and-fire modulator (IAF) topologies to improve in-pixel signal linearity in digital imagers. Three types of soft-reset schemes are analyzed for capacitive trans-impedance amplifiers (CTIAs). The proposed Type III has the main advantages of avoiding any low-impedance voltage source or extra capacitor, of including correlated double sampling (CDS) for the cancellation of CTIA low-frequency noise, and of minimum current biasing requirements. Comparative electrical simulations are also presented to demonstrate the linearity improvements of soft-reset schemes and the increase of IAF modulation robustness under low-power circuit operation.

This paper presents a highly linear current-controlled ring-oscillator (CCRO) circuit for current-to-frequency ADC in smart sensing. The proposed CCRO topology employs a distributed regulation of the oscillator rail voltage for lowering its sensitivity with respect to the controlling input current. The use of a current conveyor for this purpose ensures the stability of the current-steering control loop together with low-area and low-power overheads. A practical circuit design example is supplied in 0.18-μm 1P6M CMOS technology consisting on a 10-bit 100-kS/s ADC without the need of any digital calibration nor postcompensation technique.

This paper proposes a free and complete EDA framework for teaching CMOS full-custom design of mixed-signal integrated circuits. The presented set of EDA tools and associated physical design kit should allow students to gain hands-on experience on schematic entry, both at system and circuit levels, HDL system simulation and block specification, automatic circuit optimization, PCell-based netlist-driven layout, interactive DRC, LVS, 3D parasitics extraction, post-layout simulation and tape-out. A case study based on a ΔΣ modulator for ADC in a simple CMOS technology is supplied to illustrate the capabilities of the proposed environment. Students can easily make use of the presented EDA framework both at laboratory and at home, since all tools are available for both MS Windows and Linux platforms.

This paper presents a 96.6-dB-peak-SNDR and 50-kHz-bandwidth switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW. This performance is achieved by the introduction of Class-AB single-stage switched variable-mirror amplifiers (VMAs) combined with an optimized architecture and a 5-phase switched-capacitor scheme. The resulting 1.8-mm2delta-sigma modulator is integrated in a standard 0.18-μm 1P6M CMOS technology and reaches a Schreier figure of merit of 164.6 dB from experimental SNDR measurements without the need for any clock bootstrapping, analog calibration or digital compensation technique.

This paper presents a new family of Class-AB operational amplifier (OpAmp) circuits based on single-stage topologies with nonlinear current amplifiers. The proposed OpAmp architecture is mainly characterized by generating all Class-AB current in the output transistors only, exhibiting very low technology sensitivity and avoiding the need of any internal frequency compensation mechanism. Hence, this family of OpAmps are suitable for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load capacitance specifications. A complete OpAmp design example integrated in standard 0.18μm 1P6M CMOS technology is supplied with detailed simulation and experimental results. Compared to MOS-only state-of-art Class-AB OpAmp literature, the proposed architecture returns the highest figure-of-merit value.

This paper presents an integrated test platform for imagers, which allows their electrical characterization by directly injecting the input current in each individual pixel. The core of the proposed ITP is a matrix of controllable current sources featuring low technology dependence, together with easily scalable row and column DACs for the digital programming of every single pixel current. A 10 kfps 32×32 4 bit×4 bit ITP chip is integrated in a low-cost 2.5 μm 1M CMOS technology, reporting μA-range full-scale and background programmability and FPN levels below 5%rms. As a result, the proposed ITP achieves accurate stimulation of both image patterns and motion sequences with a compact test setup.

This paper presents a novel digital pixel architecture for MWIR PbSe sensors and high-speed AER imagers. Low-power and compact circuits are proposed for pixel built-in log-domain temporal contrast, signal adapted self-biasing, linear current to spike frequency conversion under high-speed AER communications, and digital PLL-based technology and temperature compensated tuning. The proposed CMOS design techniques make extensive use of transistor subthreshold operation and circuit reuse. The resulting 40μm-pitch digital pixel is designed in standard 0.35μm 2P4M CMOS technology, and preliminary simulation results are reported.

A novel DPS integrator scheme for fast CMOS imagers is presented, which combines the advantages of analog APS and DPS circuits. The reset-insensitive integrator proposal improves the linearity of the ADC curve, while it allows both low-power consumption for the active blocks and low-voltage operation for the switching devices even at high frame rates. In this sense, a comparative study is presented in 0.18 mum 1-poly 6-metal 1.8 V CMOS technology to demonstrate the advantages of this novel solution.

This paper presents a new low-power and fully programmable digital CMOS active pixel sensor for uncooled and fast IR imagers. The proposed self-biased topology includes built-in input capacitance compensation, mixed integration, A/D conversion and a purely digital I/O interface, all at pixel level. Furthermore, full FPN compensation is also supplied by digital tuning of the individual offset and gain of each DPS during read-out at no speed costs. Two circuit implementations for IR PbSe sensors have been integrated in standard 0.35μm CMOS 2-polySi 4-metal technology, and exhaustive experimental data is presented from electrical tests.

This paper describes xENoC, an automatic and component re-use HW-SW environment to build simulatable and synthesizable Network-on-Chip-based MPSoC architectures. xENoC is based on a tool, named NoCWizard, which uses an eXtensible Markup Language (XML) specification, and a set of modularized components and templates to generate many types of NoC instances by using Verilog HDL. This NoC models can be customized in terms of topology, tile location/mapping, RNIs generation, different types of routers, FIFO and packet/flit sizes, by simply modifying the XML specifications. Furthermore, xENoC is also composed of software components, i.e. RNI drivers and a parallel programming model, embedded Message Passing Interface (eMPI), which let us to carry out a complete HW-SW co-design methodology to design distributed-memory NoC-based MPSoCs parallel applications. Through xENoC different distributed-memory NoC-based MPSoCs designs have been created simulated and prototyped in physical platforms (e.g. FPGA boards), and some parallel multiprocessor test traffic applications are running there as system level demonstrators.

This paper presents a new low-power and compact digital active pixel sensor (APS) for hybrid CMOS imagers. The proposed self-biased topology includes built-in dark current and input capacitance compensation, mixed integration, A/D conversion and a purely digital I/O interface, all at pixel level. Furthermore, full FPN compensation and AGC capabilities are also supplied by digitally pre-programming the individual sensitivity of each APS during the read-out phase without any speed reduction. In this sense, experimental results are reported for a 100μm×100μm complete APS circuit in standard 0.35μm CMOS 2-polySi 4-metal technology for IR applications.

This paper describes a 12-bit current mode digital to analog converter. Circuit topology uses two arrays of 64 equal current sources, each one generating both the current associated to six bits, corresponding to either MSB or LSB parts. The main novelty of that topology is the method used to limit the maximum current provided by the LSB block, which ensures a monotonic behavior of the system. The circuit has been designed and fabricated using a 0.35 mum CMOS process and occupies an area of 0.17 mm2