This paper describes design techniques for ultra-low power cryogenic CMOS circuits for next generation quantum computing applications. Specifically, it discusses two generations of fully integrated analog front-end circuits realized using end-to-end current mode design techniques to realize RF control of qubits at 4K ambient temperatures, presenting design The demonstrated current mode qubit state controller designs were implemented in 14nm FinFET CMOS technology; these designs consume 23.1mW and 12.8mW respectively.

In this paper we discuss parametric measurements of devices implemented in a commercial 14nm CMOS FinFET process taken at cryogenic temperatures. The data may be used to create cryo-CMOS device models for developing CMOS control and readout circuits of qubits in quantum computer. Access to a large number of devices was enabled using an integrated digitally addressable analog multiplexer; the combination of this multiplexer and the set of devices accessible through the multiplexer forms an addressable parametric array. We will discuss the test structure, the measurement technique, the test challenges, and the device parameter shifts that we have observed, over a temperature range from 300K down to 7.9K. The addressable nature of the multiplexer allows investigation of a variety of device types in a single sample cool down. In addition, the accessibility of large numbers of devices allows statistics to be gathered on the variation of key device parameter spreads with temperature.

Future generations of quantum computers are expected to operate in a paradigm where multi-qubit devices will predominantly perform circuits to support quantum error correction. Highly integrated cryogenic electronics are a key enabling technology to support the control of the large numbers of physical qubits that will be required in this fault-tolerant, error-corrected regime. Here, we describe our perspectives on cryoelectronics-driven qubit control architectures, and will then describe an implementation of a scalable, low-power, cryogenic qubit state controller that includes a domain-specific processor and a SSB upconversion I/Q-mixer-based RF AWG. We will also describe an FPGA-based emulation platform that is able to closely reproduce the system intention, and which was used to verify different aspects of the ASIC system design in in situ transmon qubit control experiments.

This paper is a tutorial-style introduction to a special session on: Effective Voltage Scaling in the Late CMOS Era. It covers the fundamental challenges and associated solution strategies in pursuing very low voltage (VLV) designs. We discuss the performance and system reliability constraints that are key impediments to VLV. The associated trade-offs across power, performance and reliability are helpful in inferring the optimal operational voltage-frequency point. This work was performed under the auspices of an ongoing DARPA program (named PERFECT) that is focused on maximizing system-level energy efficiency.

Drawing on neuroscience, we have developed a parallel, event-driven kernel for neurosynaptic computation, that is efficient with respect to computation, memory, and communication. Building on the previously demonstrated highly optimized software expression of the kernel, here, we demonstrate True North, a co-designed silicon expression of the kernel. True North achieves five orders of magnitude reduction in energy to-solution and two orders of magnitude speedup in time-to solution, when running computer vision applications and complex recurrent neural network simulations. Breaking path with the von Neumann architecture, True North is a 4,096 core, 1 million neuron, and 256 million synapse brain-inspired neurosynaptic processor, that consumes 65mW of power running at real-time and delivers performance of 46 Giga-Synaptic OPS/Watt. We demonstrate seamless tiling of True North chips into arrays, forming a foundation for cortex-like scalability. True North's unprecedented time-to-solution, energy-to-solution, size, scalability, and performance combined with the underlying flexibility of the kernel enable a broad range of cognitive applications.

A voltage-controlled oscillator linearization technique suitable for dual-path phase-locked loops is presented. In the proposed scheme, the state of the integral control path sets the gain of a transconductor in the proportional path in such way that nearly constant VCO gain through the proportional path is achieved. A detailed analysis and design example is presented in the context of delay-interpolating ring-based VCOs. Simulation and measurements in ST 90 nm CMOS technology show that the proposed technique is effective in reducing gain variations across the VCO's tuning range from an uncompensated spread of 1:4 to an average of 1:1.3.

In 1997, the American Medical Informatics Association proposed a US information strategy that included a population health record (PopHR). Despite subsequent progress on the conceptualization, development, and implementation of electronic health records and personal health records, minimal progress has occurred on the PopHR. Adapting International Organization for Standarization electronic health records standards, we define the PopHR as a repository of statistics, measures, and indicators regarding the state of and influences on the health of a defined population, in computer processable form, stored and transmitted securely, and accessible by multiple authorized users. The PopHR is based upon an explicit population health framework and a standardized logical information model. PopHR purpose and uses, content and content sources, functionalities, business objectives, information architecture, and system architecture are described. Barriers to implementation and enabling factors and a three-stage implementation strategy are delineated.

The authors describe their efforts in developing sensorimotor chips which contain arrays of sensing elements, circuitry for processing the raw sensor data into forms relevant to motion-related tasks, circuitry for generating motion signals based on the processed sensor data and the goals of the system, and an operating system which selects a unique motor command from a set of usually conflicting motion signals. Sensors of this kind are intended for use in robots. They would greatly reduce the computational burden from that imposed with standard sensing techniques that use high bandwidth video cameras or even tactile sensing arrays, since they would generate motor signals directly rather than sensor signals from which another computer would have to generate motor signals.>