Valery A. Vardanian

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19ranked-venue papers

5as first author

1since 2021 · last 2025

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 18 · 4 first-author · 1 since 2021Software engineering, systems software and programming languages · 3 · 1 first-authorTheory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Electronic design automation › hardware verification and test fault detection	0.1	1	2012	A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation hardware verification and test	0.1	1	2012	A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › hardware verification and test › memory testing march test algorithm	0.1	1	2012	A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › hardware verification and test memory testing	0.1	1	2012	A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012

Methods — techniques the papers use, named apart from their topics

test algorithm generation · 0.1fault classification · 0.1

Year	Publication	Venue	Position
2025	European Test Symposium Teams: an Anniversary Snapshot abstract The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing. Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi 0002, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. D. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard 0001, Marcello Traiola, Arnaud Virazel, Fernando Santos 0001, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Veiras Bolzani, Milos Krstic, Marko S. Andjelkovic, Fabian Vargas 0001, Grigor Tshagharyan, Gurgen Harutunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zainalabedin Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand	ETS	57
2014	Fault modeling and test algorithm creation strategy for FinFET-based memories abstract FinFET transistors are playing an important role in modern technology that is rapidly growing. Embedded memories based on FinFET transistors lead to new defects that can require new embedded test and repair solution. To investigate FinFET-specific faults the existing models and detection techniques are not enough due to a special structure of FinFET transistors. This paper presents a new strategy for investigation of FinFET-specific faults. In addition to fault modeling, a new method is proposed for test algorithm synthesis. The proposed methodology is validated on several real FinFET-based embedded memory technologies. Moreover, new faults are identified that are specific only to FinFETs. Gurgen Harutunyan, Grigor Tshagharyan, Valery A. Vardanian, Yervant Zorian	VTS	3
2013	An effective solution for building memory BIST infrastructure based on fault periodicity abstract This paper introduces a new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms. It is proposed to describe all the periodicity and regularity rules in a form of a special Fault Periodicity Table (FPT) and March Test Template (MTT). FPT allows considering any large number of faults in one table and MTT allows obtaining March tests without using special tools for their generation. Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	VTS	3
2012	A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs abstract In this paper, all linked and unlinked static and two-operation dynamic faults are considered. A classification for their description is introduced. To generate a test algorithm for detection of all the considered faults, it was shown that it is not an easy problem. For this purpose, a new structure-oriented method is developed. Based on the proposed method, an efficient test algorithm March LSD of complexity 75N is generated for the detection of the considered linked static and dynamic faults. Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	3
2011	A Robust Solution for Embedded Memory Test and Repair abstract This paper presents a robust solution for test and repair of embedded memories. The STAR (Self-Test and Repair) Memory System solution is developed within Synopsys Design Ware allowing users to create, integrate and verify embedded memory test and repair IP in system on chips. The key components and features of the SMS are discussed. K. Darbinyan, Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	Asian Test Symposium	4
2011	Generic BIST architecture for testing of content addressable memories abstract Minimal March test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an extension of an existing BIST architecture for testing of static random access memories (SRAMs) and read-only memories (ROMs). This generic BIST architecture additionally supports the following important CAM specific features: power buffer-zones, multicycle compare operations, half/quarter words and walking patterns. Hayk T. Grigoryan, Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	IOLTS	4
2011	Symmetry Measure for Memory Test and Its Application in BIST Optimization Gurgen Harutunyan, Aram Hakhumyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	J. Electron. Test.	4
2008	An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories abstract Previously, a minimal algorithm of length 70 N, N is the number of memory bits, was proposed for a subclass of dynamic faults. In this paper, a March-based fault location and full diagnosis algorithm of complexity 88 N+29 is proposed for the same subclass of dynamic faults in bit-oriented SRAMs. Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	VTS	2
2007	Minimal March Tests for Detection of Dynamic Faults in Random Access Memories Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	J. Electron. Test.	2
2006	Minimal March Tests for Dynamic Faults in Random Access Memories abstract The class of dynamic faults has been recently shown to be an important class of faults for the new technologies of random access memories (RAM) with significant impact on DPM levels. Very little research has been done in the design of memory test algorithms targeting dynamic faults. Two March test algorithms of complexity 11N and 22N, N is the number of memory cells, for subclasses of two-operation single-cell and two-cell dynamic faults respectively were proposed earlier by other authors. Also a March test of complexity 100N was proposed by them for detection of two-cell dynamic faults with two fault-sensitizing operations both applied on the victim or aggressor cells. In this paper, for the first time, minimal March test algorithms are proposed for two-operation single-cell and two-cell dynamic faults. The previously known March test algorithm for detection of two-operation two-cell dynamic faults is improved by 30N Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	ETS	2
2006	Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories abstract In this paper, a new notion of 2-composite static faults covering all unlinked and (realistic) linked static faults is introduced. We have introduced 120 new linked fault primitives missing in the paper by Hamdioui et al (IEEE TCAD 2004), thus extending the universe of linked fault primitives known before by 25%. A march test algorithm of length 23N (N - number of memory words) for detection of linked static faults in random access memories is proposed. It reduces the length of a previously known algorithm (Hamdioui et al., IEEE TCAD 2004) by 18N. We proved the proposed test is of minimum length Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	VTS	2
2005	Impact of Soft Error Challenge on SoC Design abstract Soft errors are a major challenge to robust design. Conventionally, designs with high level requirements for reliability and availability required protection against soft errors. However, the scaling level reached with today's nanometer technologies is moving the soft error protection requirements to SoC designs for a wide range of applications. This paper discusses the soft error challenge, its implication on SoC design practices and possible approaches to create a robust SoC design. Yervant Zorian, Valery A. Vardanian, K. Aleksanyan, Karen Amirkhanyan	IOLTS	2
2005	Minimal March Tests for Unlinked Static Faults in Random Access Memories abstract New minimal March test algorithms are proposed for detection of (all) unlinked static faults in random access memories. In particular, a new minimal March MSS test of complexity I8N is introduced detecting all realistic simple static faults, as March SS (22N), (S. Hamdioui, van de Goor, Rodgers, MTDT 2002). Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	VTS	2
2004	A Methodology for Design and Evaluation of Redundancy Allocation Algorithms abstract A methodology for design and evaluation of redundancy allocation algorithms based on prime algorithms is proposed for memory devices with spare elements. The methodology can be applied to any memory device with spare elements. It allows the design of simple but effective built-in redundancy allocation (BIRA) algorithms working "on-the-fly" with BIST. The methodology allows also reasonable trade-off between repair coverage and hardware/time complexity during the implementation. A basic toolset for design and evaluation of BIRA algorithms based on the proposed methodology is developed and preliminary results of experiments on the application of the tool for self-test and repair (STAR) type SRAM memories are adduced. Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	VTS	2
2000	Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check abstract Summary form only given. A heuristic design-for-checkability method based on observation point insertion in the Circuit Under Check (CUC) is proposed to increase the error detection ability of Concurrent Checkers (CC). In particular at least 99% of error detection is obtained for parity checkers and almost all ISCAS'85 benchmark circuits by inserting 2-5 groups of observation points compacted by parity trees. Valery A. Vardanian, Liana B. Mirzoyan	DATE	1
1997	Exact probabilistic analysis of error detection for parity checkers abstract Error detection probability and latency of the parity checker with respect to single stuck-at faults in the circuit under check (CUC) are calculated analytically. A notion of "multi-output supergate" is introduced for multi-output combinational CUC generalizing the formerly known notion of (single-output) supergate. "Restricted" observabilities and detectabilities are calculated for each line in the CUC with respect to non-empty subsets of outputs of the CUC. The method may be easily extended for other concurrent checkers as well. Valery A. Vardanian	VTS	1
1996	On completely robust path delay fault testable realization of logic functions abstract A large class of Boolean functions, as well as almost all symmetric Boolean functions, are shown to have no two-level completely robust path-delay-fault testable (RPDFT) realization by combinational circuits. Exact and asymptotic formulae are derived for the number of symmetric Boolean functions which have two-level completely RPDFT realization. To achieve completely RPDFT realization, a notion of RPDFT-extension is proposed for logic functions which have no two-level completely RPDFT realization. Algorithms are devised for the design of RPDFT-extensions with at most 2 extra input variables. Valery A. Vardanian	VTS	1
1994	On the complexity of terminal stuck-at fault detection tests for monotone Boolean functions abstract Upper and lower bounds are obtained on the minimum length of tests detecting single and multiple stuck-at-0 and stuck-at-1 faults at input/output terminals of combinational logic networks realizing monotone Boolean functions of n variables.> Valery A. Vardanian	VTS	1
1985	On the length of single dynamic tests for monotone Boolean functions Valery A. Vardanian	FCT	1