EDBT 2026 Demo / reviewers in the wild / expert
Mike Paquette
dblp:35/1847
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 50% GPUs and heterogeneous computing · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing
graphics accelerator |
0.0 | 1 | 1987 | Parallel Computers for Graphics Applications · ASPLOS 1987 |
Processor architecture and microarchitecture
SIMD |
0.0 | 1 | 1987 | Parallel Computers for Graphics Applications · ASPLOS 1987 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1987 | Parallel Computers for Graphics ApplicationsabstractSpecialized computer architectures can provide better price/performance for executing image processing and graphics applications than general purpose designs. Two processors are presented that use parallel SIMD data paths to support common graphics data structures as primitive operands in arithmetic expressions. A variant of the C language has been implemented to allow high level language coding of user applications on these processors. High level programming support is designed into the processor architecture that implements parallel object data typing and parallel conditional evaluation in hardware. Adam Levinthal, Pat Hanrahan, Mike Paquette, Jim Lawson |
ASPLOS | 3 |