Sparse vector coding (SVC) is a promising short-packet transmission method for ultra reliable low latency communication (URLLC) in next-generation communication systems. In this paper, a block SVC (BSVC) based short-packet transmission scheme is proposed to further enhance the transmission performance of SVC. The core idea behind the proposed scheme is to transmit short-packet data information after block sparse transformation. At the transmitter, the information bits are divided into two parts: one part is mapped into the non-zero indexes of block sparse vectors, and the other part is mapped into non-zero values through phase or amplitude modulation. After pseudo-random spreading, the block sparse vectors are mapped to time-frequency resources for transmission. At the receiver, the decoding problem is transformed into a block sparse signal recovery problem. A cyclic block orthogonal matching pursuit (CBOMP) algorithm is proposed for decoding by leveraging block-structured sparse prior information. The upper bound of block error rate (BLER) performance over Rayleigh channels is derived to verify the decoding performance of the proposed CBOMP algorithm. Extensive simulation results verify that the proposed BSVC scheme outperforms the existing SVC schemes in terms of BLER, transmission latency and spectral efficiency over fading channels.

In this work, we construct a compact composite AES S-Box by deriving a new low multiplicative complexity GF (24) inversion circuit. A deterministic tree search algorithm is applied to search for constructions that are optimum in terms of multiplicative complexity. From the results, the circuit with the smallest gate count is selected for GF (24) inversion. To the best of our knowledge, the proposed AES S-Box requires the smallest gate count to date with the size of 112 gates and depth of 25 gates.

Owing to the importance of rolling element bearings in rotating machines, condition monitoring of rolling element bearings has been studied extensively over the past decades. However, most of the existing techniques require large storage and time for signal processing. This paper presents a new strategy based on compressive sensing for bearing faults classification that uses fewer measurements. Under this strategy, to match the compressed sensing mechanism, the compressed vibration signals are first obtained by resampling the acquired bearing vibration signals in the time domain with a random Gaussian matrix using different compressed sensing sampling rates. Then three approaches have been chosen to process these compressed data for the purpose of bearing fault classification these includes using the data directly as the input of classifier, and extract features from the data using linear feature extraction methods, namely, unsupervised Principal Component Analysis (PCA) and supervised Linear Discriminant Analysis (LDA). Classification performance using Logistic Regression Classifier (LRC) achieved high classification accuracy with significantly reduced bandwidth consumption compared with the existing techniques.

Rolling element bearings have a pivotal role in rotating machine and their failures are the leading cause of more substantial failures in the machine. In response to their importance, there is a growing body of research looking at condition monitoring of rolling element bearings to avoid machine breakdowns. In this study, by taking advantages of Compressive Sampling (CS), Laplacian Score (LS) and Multi-class Support Vector Machine (MSVM), an intelligent method for rolling bearing fault classification is proposed The CS is used to obtain compressed samples of the raw vibration signals, and the LS is used to rank the features of the obtained compressed samples with respect to their importance and correlations with the core fault characteristics. Then, based on LS ranking, we selected a small amount of the most significant compressed samples to produce the features vector. Finally, classification performance using MSVM shows high classification accuracy with a significantly reduced feature set.

Automatic fault detection and classification for roller element bearings is an important issue for rotating machine condition monitoring. In this paper, we classify roller element bearings fault classes under two and three hidden layers' deep neural network framework based on sparse Autoencoder. This allows us to learn and extract features for the bearing vibration samples in an unsupervised manner using the encoder part of the Autoencoder. Then we form the deep neural network by stacking the encoders in each stage of the hidden layers together with the softmax layer. Classification performance using the full deep network and backpropagation compared, and effects of different deep neural network parameters on the classification accuracy are studied here.

The panoramic unwrapping of catadioptric omnidirectional view (COV) sensors have mostly relied on a precomputed mapping look-up table due to an expensive computational load that generally has its bottleneck occur at solving a sextic polynomial. However, this approach causes a limitation to the viewpoint dynamics as runtime modifications to the mapping values are not allowed in the implementation. In this paper, a parallel root-finding technique using Compute Unified Device Architecture (CUDA) platform is proposed. The proposed method enables on-the-fly computation of the mapping look-up table thus facilitate in a real-time viewpoint adjustable panoramic unwrapping. Experimental results showed that the proposed implementation incurred minimum computational load, and performed at 10.3 times and 2.3 times the speed of a current generation central processing unit (CPU) respectively on a single-core and multi-core environment.

In this work, we derive three novel composite field arithmetic (CFA) Advanced Encryption Standard (AES) S-boxes of the field GF(((22)2)2). The best construction is selected after a sequence of algorithmic and architectural optimization processes. Furthermore, for each composite field constructions, there exists eight possible isomorphic mappings. Therefore, after the exploitation of a new common subexpression elimination algorithm, the isomorphic mapping that results in the minimal implementation area cost is chosen. High throughput hardware implementations of our proposed CFA AES S-boxes are reported towards the end of this paper. Through the exploitation of both algebraic normal form and seven stages fine-grained pipelining, our best case achieves a throughput 3.49 Gbps on a Cyclone II EP2C5T144C6 field-programmable gate array.