We propose an automatic wafer defect maps detection method based on unsupervised learning. There is no need for human labeling, and similar defect clusters are identified automatically without human intervention. As a result, the process is less error-prone. Whenever the wafer test result of a WUT is available, it can be compared immediately with existing clusters. If the wafer map matches one of the known defect patterns, then RCA can be done efficiently.

Test generation and fault simulation are essential in VLSI automatic test pattern generation (ATPG). Parallel computing on GPU gives another way to improve work performance. Thousands of concurrent threads can be launched simultaneously within GPU. Due to severe GPU memory limitation, scalability algorithm and efficient data transfer are necessary for test generation and fault simulation. In this paper, we present a GPU-based ATPG system that can scale memory usage and reduce data transfer between processors. We utilize several parallelism methods to enhance the system ability. Comparing to a commercial tool run with CPU in single, two, four, and eight cores, experiments show that our algorithm has 3.99, 2.18, 1.17 and 0.94 times of speedup and 0.85, 0.78, 0.76 and 0.73 times of less memory usage, respectively.

Wafer map defect pattern recognition is valuable for root cause analysis and yield learning. Most of the previous studies on defect pattern recognition are based on supervised machine learning, in which labeled wafer maps are used to train a machine learning model for automatic classification. Some problems arise in this approach. First, there may be misclassification in the original labeled data, which makes it difficult to establish an accurate prediction model. Secondly, defect patterns that are not defined before will not be classified correctly. In this paper, we proposed a semi-supervised framework to deal with these problems. Labeled wafer maps are first used to train a prediction model, with likely misclassified data excluded. The prediction model is then used to classify unlabeled data. The remaining data that cannot be properly classified are then sent to an unsupervised learning algorithm to extract more defect patterns with enhanced labeling techniques. This proposed approach is validated with TSMC 811K database, in which we are able to define five new defect pattern types. Experimental results show that total 14 defect types can be recognized with overall accuracy of 94.37%.

Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.

This paper proposes a novel type of modified Booth multiplier and generates constant test pairs for single transition delay faults (TDFs) in multipliers of various sizes. All TDFs of the multipliers at cell and gate levels are C-testable with 10 and 27 patterns, respectively. These patterns can be generated by using a linear feedback shift register or a finite state machine, requiring a modest increase of 5% area for our 32 X 32 multiplier, for example. In addition, a method is proposed to generate 51% to 99% fewer patterns for the realistic sequential cell fault model (RS-CFM), when compared with a recent work. RS-CFM faults, which are claimed to be comprehensive in modeling sequential fault effects inside the cells, require all possible single-input-change patterns prepared for each cell. The proposed method generates 104 + 10 X Ny test pairs for RS-CFM in the Nx X Nymodified Booth multiplier to achieve a similar fault coverage as the cited work.

In this paper, we discuss some strategies for identifying unrepairable memories, and from that to introduce a novel theorem that can make more precise identification. A new algorithm for searching repair solutions is also proposed, which characterizes the rows, and columns of defective memory cells with revised effective coefficients. We have simulated it on many generated example maps, and compared it with the previous algorithms to verify its efficiency. It's combined with those arranged strategies of judging unrepairability to generate a complete flow. The complete algorithm has also been run on many examples with various memory sizes, defect numbers, and distribution types. The simulation results further show that identifying unrepairability in advance can help the reconfiguration procedure run much faster than searching solutions directly.

In this paper, a flip-flop selection methodology, which utilizes reachable states of flip-flops, required states for hard-to-detect faults, which are obtained from test generation, and the structural connection relationship of flip-flops, to achieve a nearly optimal mixed partial-scan/reset design, is proposed. The methodology first generates and simulates test patterns for the circuit-under-test to obtain information of reachable states and states needed for excitation and propagation of hard-to-detect faults. It then searches the connection relationship among flip-flops and arranges flip-flops in an appropriate order for mixed partial scan and reset selection. Experimental results show that the method achieves higher testability than reported methods with a lesser number of scan/reset flip-flops.

This paper proposes a method to select flip-flops for partial reset and/or partial scan for sequential circuits to increase their testability. The method gives weights for flip-flops for consideration for partial reset and/or scan based on information on required states for activating faults and the number of faults which propagate to flip-flops, which are obtained during test generation. Since the above information offers the reasons causing the untestable and/or hard-to-detect faults, the method is very efficient in locating flip-flops for partial reset and/or scan to ease test generation task. Experiments showed that this method selected less number of flip-flops for partial reset and scan while produced more testable circuits for benchmark circuits.

For sequential circuit test pattern generation incorporating backward justification, we need to justify the values on flip-flops to activate and propagate fault effects. This takes much time when the values to be justified on flip-flops appear to be invalid states. Hence, it is desirable to know invalid states, either dynamically during the justification process or statically before proceeding to test generation. This paper proposes algorithms to identify, before test generation, invalid states for sequential circuits without reset states. The first algorithm explores all valid states from an unknown initial state to search the complete set of invalid states. The second algorithm finds the complete set of invalid states from searching the reachable states for each state. The third algorithm searches the invalid states which are required for test generation to help stop justification early by analyzing dependency among flip-flops to simulate each partial circuit. Experimental results on ISCAS benchmark circuits show that the algorithms can identify invalid states in short time. The obtained invalid states were also used in test generation, and it was shown that they improved test generation significantly in test generation time, fault coverage, and detection efficiency, especially for larger circuits and for those that were difficult to generate.

For sequential circuit test pattern generation, the information on invalid states will help greatly on backward justification to reduce the test generation time. This paper proposes three algorithms to find invalid states for sequential circuit test generation. The first two algorithms search the complete set of invalid states by exploring all valid states and reachable states respectively. The first algorithm is efficient for circuits having more invalid states than valid states while the second algorithm is efficient for circuits having more valid states than invalid states. The third algorithm searches only the invalid states that are required for test generation to stop justification early. Experimental results on ISCAS benchmark circuits show that the algorithm can identify invalid states in short time and can help improve test generation significantly in the fault coverage, detection efficiency, and generation time.