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H. C. Srinivasaiah

dblp:35/2500 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 61% Integrated circuit design · 39%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › circuit simulation
device and circuit simulation		 0.012003
Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003
Electronic design automation › technology computer-aided design
process and device simulation		 0.012003
Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003
Integrated circuit design › semiconductor devices
short-channel effects		 0.012003
Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003

Methods — techniques the papers use, named apart from their topics

process simulation · 0.0mixed-mode simulation · 0.0device simulation · 0.0
YearPublicationVenuePosition
2003 Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations
abstract
Process, device, and mixed-mode (device/circuit) simulation-based approach is presented for 0.1-/spl mu/m gate length CMOS technology optimization and sensitivity analysis. The disposable spacer-based 0.1-/spl mu/m NMOS and PMOS transistors with excellent short channel characteristics are designed using process and device simulations. The implant-dose sensitivity of the device parameters around the nominal value are estimated. The halo implant and super steep retrograde channel implant dose fluctuations are found to have a profound effect on device characteristics. It is shown that the mixed-mode device/circuit simulation can be used as an excellent tool to connect the circuit delay sensitivity to underlying process parameters. The simulation results demonstrate that the relation between circuit and process parameters is highly nonlinear for the deep submicron technology.
H. C. Srinivasaiah, Navakanta Bhat
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1