The smart sensor plays an important role for Internet of Things (IoT) development in the past few years. Due to the fast advance of IC fabrication and electronic design automation technologies, integrating a smart sensor design into a single chip has become practical. To assist the MEMS sensor teams in Taiwan academia to accelerate their smart sensor development, this paper presents a smart sensor development platform which consists of a common platform unit and a sensor unit. Our proposed smart sensor development platform provides the solutions of FPGA-based design, Smart Sensor on Chip (SSoC) design, and Smart Sensor in Package (SSiP) design for smart sensor development. The design flow and deliverables for the SSoC and SSiP smart sensor implementations are also presented in this paper. The proposed smart sensor common platform unit was taped out with UMC 0.18um process to perform the silicon proof. Moreover, this paper also presents a modularized wireless sensor system, MorSensor, to facilitate the smart sensor system demonstration. A case study for the FPGA-based smart sensor is also given in this paper. The experiment results show that the presented smart sensor platform is very suitable for smart sensor development, while MorSensor is suitable for the smart sensor system demonstration.

The role of Chip Implementation Center (CIC), founded in 1992 under the National Science Council (NSC) of Taiwan R.O.C., is to provide the services for the fabrication of multi-project chip (MPC), the procurement/integration of software CAD tools, and the promotion of IC and FPGA design/testing/CAD software technology for academia in Taiwan. To date, CIC assisted 86 universities and polytechnics to install over 6000 academic licenses of FPGA design and verification tools. Moreover, CIC promotes various training courses intensively and periodically for the FPGA design flow. In year 2002, 8 kinds of courses with over 25 classes are provided to meet the demands from academia sites. More than 1000 students are trained in these classes. The FPGA design flow, provided by CIC, is used in many of researches for implementation, verification, and prototypes. Based on the demands of academics, CIC will build a laboratory for rapid prototyping system-level design. In this laboratory, SoC (System on a Chip) and IP (Intellectual Property) designs can be downloaded into FPGA to work with a processor to verification on an SOPC (System on Programmable Chip) environment.

FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, congestion, etc) based on geometric distance and/or channel density is no longer accurate for FPGAs. Researchers have shown that the number of segments, instead of geometric (Manhattan) distance, traveled by a net is the most crucial factor in controlling the routing delay and cost in an FPGA. Further, the congestion information of a routing channel shall be measured by the available segments of specific lengths, instead of the density in a channel alone. In this paper, we propose an architecture-driven metric for simultaneous FPGA placement and global routing. The new metric considers the available segments and their lengths to optimize the wiring cost for placement and global routing. Experiments by employing a cluster growth placement and maze routing to demonstrate the new metric show respective average reductions of 8%, 20%, and 19% in the number of tracks used (area), maximum net delay, and average net delay based on the Lucent Technologies ORCA2C-like and the Xilinx XC4000EX-like architectures, compared with the traditional metric of geometric distance and channel density.