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Sunil Ashtaputre

dblp:35/2832 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Algorithms and data structures · 50% Graph algorithms and graph theory · 50%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Parallel and multicore computing · 23%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
systolic array
0.011985
Systolic Arrays with Embedded Tree Structures for Connectivity Problems · IEEE Trans. Computers 1985
Graph algorithms and graph theory
connectivity problems
0.011985
Systolic Arrays with Embedded Tree Structures for Connectivity Problems · IEEE Trans. Computers 1985
Algorithms and data structures › data structure design
union-find
0.011985
Systolic Arrays with Embedded Tree Structures for Connectivity Problems · IEEE Trans. Computers 1985
Parallel and multicore computing
parallel algorithms
0.011985
Systolic Arrays with Embedded Tree Structures for Connectivity Problems · IEEE Trans. Computers 1985
YearPublicationVenuePosition
1996 A New Faster Algorithm for Iterative Placement Improvement
abstract
We present a new faster design-style independent iterative placement improvement algorithm. Randomized simulated annealing based algorithms produce good result. But on very large designs, the inherently long run-time makes it prohibitive to use randomized algorithm. On the other hand deterministic improvement methods do not produce as good a result as the simulated annealing based algorithms. Moreover, none of the existing placement improvement techniques addresses the non row-based design style. In this paper, we combine the advantages of both the random and deterministic approach to develop a new faster placement improvement algorithm. Experimental results show that our algorithm performs much better than existing placement improvement algorithm. On some benchmarks, our algorithm is as much as 8/spl times/ faster than that on Domino with a significant reduction in total net length.
Moazzem Hossain, Bala Thumma, Sunil Ashtaputre
Great Lakes Symposium on VLSI3
1985 Systolic Arrays with Embedded Tree Structures for Connectivity Problems
abstract
We show how tree structures can be embedded in a one-dimensional systolic array to solve a connectivity problem, the UNION-FIND problem, by a single left-to-right pass of the data through the array. A previous solution, which did not use trees, required a left-to-right pass followed by a right-to-left pass through the array, as well as a more complex program for each cell.
Sunil Ashtaputre, Carla D. Savage
IEEE Trans. Computers1