The testability problem of dual-port memories is investigated. A functional model is defined, and architectural modifications to enhance the testability of such chips are described. These modifications allow multiple access of memory cells for increased test speed with minimal overhead on both silicon area and device performance. New fault models are proposed, and efficient O(/spl radic/n) test algorithms are described for both the memory array and the address decoders. The new fault models account for the simultaneous dual-access property of the device. In addition to the classical static neighborhood pattern-sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, duplex dynamic neighborhood pattern-sensitive faults (DDNPSF).

Merged Current Switch Logic (MCSL) and Differential Cascode Voltage Switch Logic (DCVSL) are two common structures for differential BiCMOS logic family, that have several potential applications in high-speed VLSI circuits. This paper studies the fault characterization of these BiCMOS circuits. The impact of each possible single defect on the behavior of the circuits is analyzed by simulation. A new class of faults which is unique to differential circuits is identified and its testability is assessed. We propose a design-for-testability method that facilitates testing of this class of faults. Two different realizations for this method are introduced. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.>

The testability problem of dual port memories is investigated. Architectural modifications which enhance testability with minimal overhead on both silicon area and device performance are described. New fault models for both the memory array and the address decoders are proposed and efficient O(/spl radic/n) test algorithms are presented. The new fault models account for the simultaneous dual access property of the device. In addition to the classical static neighborhood pattern sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, Duplex Dynamic Neighborhood Pattern Sensitive faults (DDNPSF).

Dynamically self-checked or fault-tolerant realizations of switching functions and sequential machines are proposed under a fault model that permits arbitrary logic faults in a single-logic module, where the modules are explicitly defined. These realizations permit considerable logic sharing, organized around an (n, m, r)-basis for decomposing switching functions. The logic sharing permits more economical realizations than can be obtained using classical parity and triple-modular redundancy schemes for obtaining logic circuits with the corresponding property.

Universal base functions (UBF's) which are generalizations of universal logic functions are defined. An (n, m, r)-UBF can be implemented as a single module (UBM) with n+m inputs and 1 output. An arbitrary n-variable switching function fn(X) is then realized on the fixed UBM by realizing a suitable set of m r-variable functions with which to drive m inputs of the UBM, the remaining n inputs being driven by X. The fan-in of a UBM for r ≥2 is shown to be considerably less than that of a universal logic module (a special case corresponding to r = 1). Specific UBF's are proposed for r = 2 in which m is on the order of 60 percent of the value obtained by using the UBF defined by the familiar Shannon decomposition formula. This is close to the theoretical lower bound on m. The use of UBM's provides a new way to realize an arbitrary function or set of functions, completely specified or otherwise, by assembling a small number of circuits selected from a small set of standard logic modules of limited fan-in. For the case r = 2, the number of two-input devices required to drive the m inputs of the UBM is often considerably less than m. DON'T CARES can be used to advantage to reduce this number still further.