Low-cost light-scattering particulate matter sensors are often advocated for dense monitoring networks. Recent literature has focused on evaluating their performance. Nonetheless, low-cost sensors are also considered unreliable and imprecise. Consequently, exploring techniques for anomaly detection, resilient calibration, and improvement of data quality should be more discussed. In this study, we analyze a year-long acquisition campaign by positioning 56 low-cost light-scattering sensors near the inlet of an official particulate matter monitoring station. We use the collected measurements to design and test a data processing pipeline composed of different stages, including fault detection, filtering, outlier removal, and calibration. These can be used in large-scale deployment scenarios where the quantity of sensors data can be too high to be analyzed manually. Our framework also exploits sensor redundancy to improve reliability and accuracy. Our results show that the proposed data processing framework produces more reliable measurements, reduces errors, and increases the correlation with the official reference.

In-memory key-value stores have quickly become a key enabling technology to build high-performance applications that must cope with massively distributed workloads. In-memory key-value stores (also referred to as NoSQL) primarly aim to offer low-latency and high-throughput data access which motivates the rapid adoption of modern network cards such as Remote Direct Memory Access (RDMA). In this paper, we present the fundamental design principles for exploiting RDMAs in modern NoSQL systems. Moreover, we describe a break-down analysis of the state-of-the-art of the RDMA-based in-memory NoSQL systems regarding the indexing, data consistency, and the communication protocol. In addition, we compare traditional in-memory NoSQL with their RDMA-enabled counterparts. Finally, we present a comprehensive analysis and evaluation of the existing systems based on a wide range of configurations such as the number of clients, real-world request distributions, and workload read-write ratios.

Particulate Matter (PM) air pollution has received growing attention in recent years due to the increased sensitivity to the problem and the spread of low-cost sensing devices. These low-cost devices are able to produce valuable data, but they come with certain hurdles which are engineering challenges to be overcome. These challenges are mainly: reduction of consumed energy; reduction of data logged and transmitted; aging of sensors. The aim of this paper is to understand if it is possible to reduce the duty-cycle of an air pollution monitoring sensor and still get meaningful data on the general behavior. This has advantages from all perspectives: it enables less logging of redundant information; it reduces the strain of the sensor to extend its lifespan and to reduce maintenance costs; it reduces the energy consumed by the sensor, essential in battery-powered devices.

In-memory key-value stores have quickly become a key enabling technology to build high-performance applications that must cope with massively distributed workloads. In-memory key-value stores (also referred to as NoSQL) primarly aim to offer low-latency and high-throughput data access which motivates the rapid adoption of modern network cards such as Remote Direct Memory Access (RDMA). In this paper, we present the fundamental design principles for exploiting RDMAs in modern NoSQL systems. Moreover, we describe a break-down analysis of the state-of-the-art of the RDMA-based in-memory NoSQL systems. In addition, we compare traditional in-memory NoSQL with their RDMA-enabled counterparts.

The computing continuum's actual trend is facing a growth in terms of devices with any degree of computational capability. Those devices may or may not include a full-stack, including the Operating System layer and the Application layer, or just facing pure bare-metal solutions. In either case, the reliability of the full system stack has to be guaranteed. It is crucial to provide data regarding the impact of faults at all system stack levels and potential hardening solutions to design highly resilient systems. While most of the work usually concentrates on the application reliability, the special session aims to provide a deep comprehension of the impact on the reliability of an embedded system when faults in the hardware substrate of the system stack surface at the Operating System layer. For this reason, we will cover a comparison from an application perspective when hardware faults happen in bare metal vs. real-time OS vs. general-purpose OS. Then we will go deeper within a FreeRTOS to evaluate the contribution of all parts of the OS. Eventually, the Special Session will propose some hardening techniques at the Operating System level by exploiting the scheduling capabilities.

Air pollution, in particular due to particulate matter, is considered a critical issue, and it is receiving ever growing attention. Environmental monitoring is not limited to the outdoor case in crowded cities, but it is also usefully applied to indoor cases such as factories and offices, or in indoor/outdoor mixed case, such as construction sites or in general industrial plants. This paper describes the case study of an environmental monitoring system, which is compliant with Internet of Things domain. In particular it is suitable for indoor/outdoor industrial applications focused on Particulate Matter measurements. In order to create a reference model, a PM10/PM2.5 sensor not yet tested in literature is used, the Honeywell HPMA115S0-XXX. Four PM10/PM2.5 sensors are used together to test repeatability. This device turned out to be effective in esteeming the level of pollution using low cost sensors, as an alternative to expensive and not portable professional devices. The implementation proposed in this paper is able to give high R values of linear regression, guaranteeing at the same time low cost in terms of hardware and low power consumption.

Ongoing emphasis on the fourth industrial revolution requires further focus on the Internet of Things (IoT) as a means to integrate all relevant entities within a single technological system. In the integration process, a gateway to relay the raw data to an IoT endpoint is essential so that a joint interface among the heterogeneous domains can be provided. This work describes the development of a distributed industrial IoT gateway, called DIIG, able to relay industrial network data to a centralized data-store. DIIG exploits a real-time client server programming model based on S7 communication and Modbus TCP protocols. The subsequent analysis carried out on the testbed mainly focuses on the performance evaluation of the gateway. In order to achieve high performance data transmission in a fair environment, a parallel real-time communication mechanism has been proposed.

Human gait is a dynamic biometrical feature that describes the kinematics of human walking. Gait modeling is studied in order to find a pattern of walking that can be used for diagnosis of walking disorder or abnormal walk detection. Difficulty in walking progressively increases with aging and causes unintentional falls, which is a common incident among elderly people. Fall prediction systems can help to prevent unintentional falls that could cause serious injuries, therefore they can reduce the health service costs. This paper presents an algorithm with polynomial classification model of human gait for real-time fall prediction. This approach enables the user to detect the transition from a normal to an abnormal walking pattern. A dataset based on the state-of-the-art techniques in simulating abnormal walks was created by using an accelerometer embedded in a smartphone, which is recognized to be precise enough for fall avoidance systems. The proposed approach improves state-of-the-art fall prediction approaches, by achieving 99.2% of accuracy in abnormal walk detection.

The majority of security systems for wireless sensor networks are based on symmetric encryption. The main open issue for these approaches concerns the establishment of symmetric keys. A promising key distribution technique is the random predistribution of secret keys. Despite its effectiveness, this approach presents considerable memory overheads, in contrast with the limited resources of wireless sensor networks. In this paper, an in-depth analytical study is conducted on the state-of-the-art key distribution schemes based on random predistribution. A new protocol, called q-s-composite, is proposed in order to exploit the best features of random predistribution and to improve it with lower requirements. The main novelties of q-s-composite are represented by the organization of the secret material that allows a storing reduction, by the proposed technique for pairwise key generation, and by the limited number of predistributed keys used in the generation of a pairwise key. A comparative analysis demonstrates that the proposed approach provides a higher level of security than the state-of-the-art schemes.

Symmetric encryption is the most widely adopted security solution for wireless sensor networks. The main open issue in this context is represented by the establishment of symmetric keys. Although many key management schemes have been proposed in order to guarantee a high security level, a solution without weaknesses does not yet exist. An important class of key management schemes is based on a transitory master key (MK). In this approach, a global secret is used during the initialization phase to generate pair-wise keys, and it is deleted during the working phase. However, if an adversary compromises a node before the deletion of the MK, the security of the whole network is compromised. In this paper, a new key negotiation routine is proposed. The new routine is integrated with a well-known key computation mechanism based on a transitory master secret. The goal of the proposed approach is to reduce the time required for the initialization phase, thus reducing the probability that the master secret is compromised. This goal is achieved by splitting the initialization phase in hierarchical subphases with an increasing level of security. An experimental analysis demonstrates that the proposed scheme provides a significant reduction in the time required before deleting the transitory secret material, thus increasing the overall security level. Moreover, the proposed scheme allows to add new nodes after the first deployment with a suited routine able to complete the key establishment in the same time as for the initial deployment.

Wireless devices are mainly used in mobile systems because they do not need any physical connection for the communication and the energy supply. Therefore, reducing the power consumption of their batteries is a critical task in order to prolong their lifetime. The main aim of this paper is to dynamically adjust both the sleeping time and the transmission power of mobile devices in an IEEE 802.11 wireless network in order to reduce the power consumption. The algorithm runs on the access point that provides the wireless connection to the devices, so no extra circuitry or computation is required to the devices. The proposal is validated through simulations, which show a battery life 20% higher than other state-of-the-art approaches.

Wireless Sensor Networks (WSNs) are increasingly used in different application fields thanks to several advantages such as cost-effectiveness, scalability, flexibility and self-organization. A hot research topic concerns the study of algorithms and mechanisms for reducing the power consumption of the nodes in order to maximize their lifetime. To this end, this paper proposes an approach based on two fuzzy controllers that determine the sleeping time and the transmission power. Simulation results reveal that the device lifetime is increased by 30% with respect to the use of fixed sleeping time and transmission power and by 25% with respect to a state-of-the-art work that adjusts only the sleeping time.

Wireless sensor networks offer benefits in several applications but are vulnerable to various security threats, such as eavesdropping and hardware tampering. In order to reach secure communications among nodes, many approaches employ symmetric encryption. Several key management schemes have been proposed in order to establish symmetric keys. The paper presents an innovative key management scheme called random seed distribution with transitory master key, which adopts the random distribution of secret material and a transitory master key used to generate pairwise keys. The proposed approach addresses the main drawbacks of the previous approaches based on these techniques. Moreover, it overperforms the state-of-the-art protocols by providing always a high security level.

When numerous RFID readers are placed in the same area, they may interfere with each other due to the reader collision problem. In recent years, many studies have been presented to address the reader collision problem. However, there is no consonance on the interference model to use in the analysis of the protocols. The main adopted models are the single interference model, which is simple and fast, but only considers the readers within a threshold distance, and the additive interference model, which sums the interferences of all the concurrent interrogations. Recent studies have shown that the single interference model cannot detect a relevant part of the possible collisions detected by the additive one. This paper analyzes and compares the network performance of an RFID system by applying both the models. Considering two proposed scenarios, the performance of the two models are evaluated and presented.

Dense passive radio frequency identification (RFID) systems are particularly susceptible to reader collision problems, categorized by reader-to-tag and reader-to-reader collisions. Both may degrade the system performance decreasing the number of identified tags per time unit. Although many proposals have been suggested to avoid or handle these collisions, most of them are not compatible with current standards and regulations, require extra hardware and do not make an efficient use of the network resources. This paper proposes the Geometric Distribution Reader Anti-collision (GDRA), a new centralized scheduler that exploits the Sift geometric probability distribution function to minimize reader collision problems. GDRA provides higher throughput than the state-of-the-art proposals for dense reader environments and, unlike the majority of previous works, GDRA is compliant with the EPCglobal standard and ETSI EN 302 208 regulation, and can be implemented in real RFID systems without extra hardware.

The reader-to-reader collision problem represents a research topic of great recent interest for the radio frequency identification (RFID) technology. Among the state-of-the-art anticollision protocols, the ones that provide high throughput often have special requirements, such as extra hardware. This study investigates new high throughput solutions for static RFID networks without additional requirements. In this paper, two contributions are presented: a new configuration, called Killer, and a new protocol, called distributed color noncooperative selection (DCNS). The proposed configuration generates selfish behavior, thereby increasing channel utilization and throughput. DCNS fully exploits the Killer configuration and provides new features, such as dynamic priority management, which modifies the performance of the RFID readers when it is requested. Simulations have been conducted in order to analyze the effects of the innovations proposed. The proposed approach is especially suitable for low-cost applications with a priority not uniformly distributed among readers. The experimental analysis has shown that DCNS provides a greater throughput than the state-of-the-art protocols, even those with additional requirements (e.g., 16 percent better than NFRA).

Supply chain is a typical scenario of exploiting Radio Frequency Identification (RFID) technology. Its growing use in all the supply chain areas makes the presence of many close RFID readers more common. In such environment, interferences among readers are critical. Many protocols have been proposed to reduce reader-to-reader collisions. Experimental data showed that the Neighbor Friendly Reader Anticollision (NFRA) protocol (IEEE Trans. Ind. Electron., vol. 56, no. 7, pp. 2326-2336, July 2009) maximizes the network throughput. However, it does not take into account the delay between the request and the granting of query tags, causing delays for some readers. This paper proposes two approaches to increase the fairness and ensure a high throughput for each reader. A theoretical analysis, supported by experimental simulations, demonstrates the improvements achieved.

The path of the information flow in Wireless Sensor Networks (WSNs) depends on the application and the particular requirements of the network. While tree-based routing algorithms are able to cope with most of the demands of periodic monitoring, a flooding protocol is necessary when the information should reach every node of the network. Opportunistic flooding is a novel protocol to flood information in WSNs which considers unreliable wireless links. It achieves good performance concerning flooding delay and energy consumption while exploiting low-duty-cycling protocols. In this work, a deep evaluation and characterization of the opportunistic flooding protocol is presented considering reliable and unreliable transmission schemes. Performance analysis is evaluated for the two mechanisms based on acknowledgments and probabilistic retransmissions. Simulation results under multiple scenarios show the behavior of the two mechanisms in different environments while providing a frame of reference to choose one scheme based on the application requirements.

Nowadays, several kinds of applications based on Radio Frequency Identification (RFID) employ a large number of tags and readers, involving collision problems. A relevant group of reader-to-reader anti-collision protocols are based on time division. Normally these protocols do not require special readers or additional entities; their main challenge is the collision resolution, since after a collision, readers have to choose a new time slot trying to avoid new collisions.It is observed that after a collision, its slot is often unoccupied, therefore this paper proposes to introduce the slot change probability as an additional parameter, in order to reduce the number of readers that change slot and the number of colliding transmissions. A new version of Distributed Color Selection (DCS) is presented, analyzed and compared with well-known protocols based on time division. The simulation analysis shows that the average time required to transmit may be reduced by over 10%.

In this paper an agri-food traceability system based on public key cryptography and Radio Frequency Identification (RFID) technology is proposed. In order to guarantee safety in food, an efficient tracking and tracing system is required. RFID devices allow recording all useful information for traceability directly on the commodity. The security issues are discussed and two different methods based on public cryptography are proposed and evaluated. The first algorithm uses a nested RSA based structure to improve security, while the second also provides authenticity of data. An experimental analysis demonstrated that the proposed system is well suitable on PDAs too.

RFID technology increases rapidly its applicability in new areas of interest without guaranteeing security and privacy issues. This paper presents a new architecture of an RFID transponder with cryptographic capabilities. Other than being compatible with the EPC Class-1 Gen-2 communication protocol, our tag implements an asymmetric ciphering module that proved useful in authentication and anti-counterfeit schemes, particularly critical in many application fields. Experimental results concerning area requirements and power consumption indicate its feasibility.

Embedded memory modules are sensitive components that deeply influence production yield of integrated devices. For fast yield improvement, an efficient manufacturing test must supply advanced defect characterization that helps in discovering technology weaknesses and finding strategies for improvement. This paper presents an industrial workflow for embedded memory diagnosis. It is based on the integration of March-based diagnostic BIST hardware in an IEEE 1500-compliant environment, and on a novel diagnostic algorithm for determining the fault model associated to the retrieved syndromes. An experimental implementation showing the feasibility of the approach is presented

Modern systems-on-chip (SoCs) allow integrating many different functional cores in the same piece of silicon. Their test requires taking fast decisions in the selection of structures and strategies at different stages of the design flow: early computation of area overhead, power consumption and test application time are indispensable in order to develop effective and efficient test for the overall chip, while taking into account physical constraints imposed by the available test equipment. Furthermore, once the test strategy has been selected and patterns generated for each module, additional nonnegligible effort is required to integrate the test program in an ATE-readable format. In this paper, we tackle these problems by means of a new software platform, leveraging descriptions of both the core-level test structure and the system-level requirements. Experimental results related to a realistic case of study underline the effectiveness of the tool and its potentialities in the IEEE 1500 environments

Determining the relation between defects and faults (fault diagnosis) in digital circuits is a key concept for semiconductors production yield improvement. Nowadays, fault diagnosis requires heavy computations and large data structures. This paper proposes a novel technique for reducing fault dictionary size for combinational and scanned circuits by means of pattern-ordering. The proposed algorithm manipulates conventional tree-based fault dictionaries. In such structures, faults are diagnosed by traversing the tree from its root to a leaf; we aim at globally reducing the length of such paths by a modified patterns order, thus also reducing the dictionary size. This approach does not cause any loss of information, since it is demonstrated for combinational circuits that the ability of a pattern set in diagnosing faults remains unaltered when modifying the patterns order. The effectiveness of the proposed approach is demonstrated for a set of sequential benchmarks equipped with scan chains.

Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.

In sub-micron technology circuits high integration levels coupled with the increased sensitivity to soft errors even at ground level make the task of guaranteeing systems' dependability more difficult than ever. In this paper we present a new approach to detect control-flow errors by exploiting a low-cost infrastructure intellectual property (I-IP) core that works in cooperation with software-based techniques. The proposed approach is particularly suited when the system to be hardened is implemented as a system-on-chip (SoC), since the I-IP can be added easily and it is independent on the application. Experimental results are reported showing the effectiveness of the proposed approach.

Discriminating between good and faulty chips is often not enough during IC manufacturing phases, where a complete understanding about failure mechanisms is required to ramp up production yield. When considering embedded memories, information about the whole set of faults needs to be extracted from the IC and processed: this asks for solutions supporting high data volume transfer. We propose an embedded architecture allowing efficient diagnosis of SoCs containing several BISTed memory cores, which minimizes ATE memory requirements for pattern storage and drastically speeds up the complete diagnostic procedure. Experimental results highlight the convenience of the approach with respect to alternative ATE driven procedures, while resorting to negligible area overhead.

Today's complex system-on-chip integrated circuits include a wide variety of functional IPs whose correct manufacturing must be guaranteed by IC producers. Infrastructure IPs are increasingly often inserted to achieve this purpose; such blocks, explicitly designed for test, are coupled with functional IPs both to obtain yield improvement during the manufacturing process and to perform volume production test. In some fields (e.g., the automotive one) there is a strong need for flexible and reusable test architectures able to guarantee effective and low-cost solutions for mission-mode fault detection capabilities within complex SoCs. In this paper, we propose to reuse structures inserted to support the manufacturing test to perform non-concurrent on-line test of SoCs. The feasibility of this approach and its costs have been evaluated on a real case of study including processor, memory and user defined logic cores.

This paper analyses the effects of single event upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools dealing with the device configuration memory, we were able to make hypothesis on the meaning of every bit in the configuration memory. From the other side, radiation testing was exploited to validate the hypothesis and to gather experimental evidence about the correctness of the obtained results. As a major result, we can provide detailed information about the effects of SEUs affecting the configuration memory of a commercial FPGA device. As a second contribution, we describe a method for obtaining the same result with similar devices. Finally, the obtained results are crucial to allow the possible usage of SRAM-based FPGAs in safety-critical environments, e.g., by working on the place and route strategies of the supporting tools.

This paper addresses the issue of diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper. The proposed solution exploits a hardware-implemented compression method that minimizes the amount of data to be transferred from the core to the ATE. The proposed solution takes into account several constraints existing in an industrial environment, such as reducing the time and area overheads required for diagnosis, and minimizing the cost of the external ATE. Experimental results are provided allowing evaluating the benefits and limitations of the adopted solution.

Commercial-off-the-shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new method for assessing the effects of SEUs in the device configuration memory. The method combines radiation testing for technology characterization and simulation-based fault injection for SEU propagation. Experimental results we gathered with the purpose of modeling the effects of SEUs in the FPGA configuration memory are reported and commented.

This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a programmable BIST approach and is able to support both testing and diagnosis. Experimental results are provided allowing to evaluate the benefits and limitations of the adopted solution and to compare it with previously proposed ones. The solution takes into account several constraints existing in an industrial environment, such as minimizing the cost of test development, easing the reuse of the available architectures for test and diagnosis of different memory types and minimizing the cost of the external ATE.

This article addresses the problem of initializing synchronous sequential circuits, that is, of generating the shortest sequence able to drive the circuit to a known state, regardless of the initial state. Logic initialization is considered, being the only one compatible with current commercial tools. A hybrid Genetic Algorithm is proposed, which combines general ideas from evolutionary computation with specific techniques, well suited to the addressed problem. For the first time, experimental results provide data about the complete set of ISCAS'89 circuits, and show that, despite the inherent algorithm incompleteness, the method is capable of finding the optimum result for the considered circuits. A prototypical tool implementing the algorithm found better results than previous methods.

This paper deals with the diagnosis of faulty embedded RAMs and outlines the solution which is currently under evaluation within STMicroelectronics. The proposed solution exploits a BIST module implementing a March algorithm, defines a wrapper allowing its interface with a TAP controller, and describes a diagnostic procedure running in the external ATE software environment. The approach allows one to test multiple modules in the same chip through a single TAP interface and is compliant with the proposed P1500 standard for Embedded Core Test. Some preliminary experimental results gathered using a sample circuit are reported, showing the effectiveness of the proposed solution in terms of area and time requirements.

In this paper we propose an approach to speed-up fault injection campaigns for the evaluation of dependability properties of processor-based systems. The approach exploits FPGA devices for system emulation, and new techniques are described, allowing emulating the effects of faults and to observe faulty behavior. The proposed approach combines the speed of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that speed-up figures up to 3 orders of magnitude with respect to state-of-the-art simulation-based techniques can be achieved.

This paper deals with a software modification strategy allowing the on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is particularly suited for low-cost safety-critical microprocessor-based applications. Experimental results from software and hardware fault injection campaigns are presented and discussed, demonstrating the effectiveness of the approach in terms of fault detection capabilities.

The widespread adoption of embedded microprocessor-based systems for safety critical applications mandates the use of co-design tools able to evaluate system dependability at every step of the design cycle. In this paper, we describe how fault injection techniques have been integrated in an existing co-design tool and which advantages come from the availability of such an enhanced tool. The effectiveness of the proposed tool is assessed on a simple case study.

In the last decade, researchers devoted much effort to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. However, during test application, circuits are subjected to an activity level higher than the normal one: the extra power consumption due to test application may thus cause severe hazards to circuit reliability. Moreover, it can dramatically shorten battery life when periodic testing of battery-powered systems is considered. In this paper we propose an algorithm to design a test pattern generator based on cellular automata for testing combinational circuits that effectively reduces power consumption while attaining high fault coverage. Experimental results show that our approach reduces the power consumed during test by 34% on average, without affecting fault coverage, test length and area overhead.

Tools for evaluating the worst-case peak power consumption of sequential circuits are highly useful to designers of low-power circuits. Previously proposed methods search for the initial state and the couple of vectors with maximum consumption, without fully considering the reachability of the initial state. This paper shows that this approach can lead to a significant underestimation of the maximum peak power consumption and proposes a new algorithm that overcomes this drawback. Experimental results show that for many circuits the algorithm is able to provide better results than those known up to now, while an approximate version is able to deal even with the largest benchmark circuits.

Fault injection is a viable solution for verifying the correct design and implementation of fault tolerance mechanisms at different levels (hardware and software). The paper discusses the use of the background diagnostic mode (BDM), available on several Motorola microprocessors and microcontrollers, for implementing a fault injection environment. BDM is well suited to implement some of the most critical operations required by a fault injection environment, such as activating the injection procedure, injecting the fault in memory or registers, and observing the faulty system behavior. The characteristics of a BDM-based fault injection environment in terms of intrusiveness, flexibility, time efficiency, and system requirements are analyzed. The authors exploit a prototypical environment they implemented to validate this analysis. As a result, the approach appears to be well suited for implementing low-cost fault injection experiments on simple embedded microprocessor- and microcontroller-based boards. Some limitations are also outlined, mostly in terms of execution time slow-down.

Evaluating the faulty behaviour of low-cost microprocessor-based boards is an increasingly important issue, due to their usage in many safety critical systems. To address this issue, the paper describes a software-implemented fault injection system based on the trace exception mode available in most microprocessors. The architecture of the complete fault injection environment is proposed, integrating modules for generating a fault list, for performing their injection and for gathering the results, respectively. Data gathered from some sample benchmark applications are presented The main advantages of the approach are low cost, good portability, and high efficiency.

This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the test pattern generation phase and selects a subset of sequences able to reduce the consumed power without reducing the fault coverage. The method is composed of three independent steps: redundant test pattern generation, power consumption measurement, optimal test sequence selection. The experimental results gathered on the ISCAS benchmark circuits show that our approach decreases the power consumption by 70% on average with respect to the original test pattern, generated ignoring the heat dissipation problem.

Evaluating the faulty behavior of low-cost embedded microprocessor-based boards is an increasingly important issue, due to their adoption in many safety critical systems. The architecture of a complete Fault Injection environment is proposed, integrating a module for generating a collapsed list of faults, and another for performing their injection and gathering the results. To address this issue, the paper describes a software-implemented Fault Injection approach based on the Trace Exception Mode available in most microprocessors. The authors describe EXFI, a prototypical system implementing the approach, and provide data about some sample benchmark applications. The main advantages of EXFI are the low cost, the good portability, and the high efficiency

This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimization algorithm is proposed, which is able to explore the trade-off between them. The algorithm is based on a newly proposed power estimation function, and on an estimate of the expected rest length of a pseudo-random rest session. Given these estimates a Genetic Algorithm, exploiting some symbolic computations with BDDs, provides a state reencoding for the circuit. The algorithm is experimental shown both to provide good results from the power optimization point of view, and to be able to sacrifice, on the designer's request, some of the power and area optimization in favor of testability improvement.

Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate initialization sequences. This paper follows the latter approach, and presents a new method to the automated generation of an initialization sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length. Finally, this paper shows how the initialization sequences can be fruitfully exploited by simplifying the ATPG process.

The constantly increasing circuit size makes the sequential ATPG problem a challenging area even when simulation-based algorithms are exploited. Several techniques have been proposed which mainly resort to logic simulation, reverting to fault simulation only when strictly required. In this paper we present a new Genetic Algorithm-based test generation method which exploits information coming from a logic simulator (e.g., the circuit activity and the reached states) to guide the search process, in particular in the fault excitation phase. Experimental results show the effectiveness of the proposed method when compared with other Genetic Algorithm-based test generators.

This paper presents a new approach to the automated generation of an initialization sequence for synchronous sequential circuits. Finding an initialization sequence is a hard task when a global reset signal is not available, and functional techniques often cannot handle large circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results we provide shore that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length.

This paper tackles the problem of analyzing the correctness and performance of a computer network protocol. Given the complexity of the problem, no currently used technique is able to achieve good results: formal techniques can discover some bugs but can be applied to over-simplified models, only; on the other hand, statistical techniques relying on simulation often fail to find some critical cases for the protocol. Our proposed approach relies on coupling a genetic algorithm with a simulator of the system under verification. Genetic algorithms recently proved themselves excellent tools for giving good, yet approximate, solution to hard-to-solve problems. To prove the effectiveness of our approach, we applied it to the quantitative verification of a network protocol: the complexity of this problem prevents the application of exact techniques, while experimental results show that the verification results we obtained are better than one can achieve with traditional statistical methods. As an example, the approach is applied to the verification of the TCP protocol operating on a given network. A genetic algorithm is able to find a configuration of the traffic over the network that sensitizes a critical problem in the TCP protocol.

Proposes an optimization algorithm for reducing the power dissipation in a sequential circuit. The encoding of the different states in a finite-state machine is modified to obtain a functionally equivalent circuit that exhibits a reduced power dissipation. The algorithm is based on a newly-proposed power estimation function that is able to quickly give an accurate estimate of the dissipated power without actually synthesizing the circuit. Given this estimate, a genetic algorithm provides a state re-encoding for the circuit. The estimation function is computed in a very efficient way by exploiting some symbolic computations with binary decision diagrams. The algorithm is experimentally shown to provide good results from the power optimization point of view, at a limited cost in terms of area increase, when compared with similar approaches.

The goal of this paper is-to compare from an experimental point of view the performance of three ATPG tools for synchronous sequential circuits. The three tools are stare-of-the-art implementations of the topological, symbolic, and GA-based approaches, respectively. The environment set up for obtaining a fair comparison is described: the same hardware platform, circuit and fault list description, and detection mechanism are adopted. The obtained results allow the reader to more deeply understand the characteristics and relative advantages/disadvantages of these methods.

The partial scan approach is now widely adopted and several commercial tools support this technique. However, there is no general agreement on how to select the scan flip flops, in general each technique is tailored to a particular ATPG algorithm and results effective when coupled with the right ATPG tool. In this paper, we propose an approach suitable for GA-based ATPGs, which is barred on exploiting some information coming from the ATPG itself we compare the results of our method with the ones of the approach based on cutting the topological loops and use a GA-based ATPG to demonstrate its effectiveness in terms of fault coverage and CPU time.

This paper deals with automated test pattern generation for large synchronous sequential circuits and describes an approach based on genetic algorithms. A prototype system named GATTO is used to assess the effectiveness of the approach in terms of result quality and CPU time requirements. An account is also given of a distributed version of the same algorithm, named GATTO*. Being based on the PVM library, it runs on any network of workstations and is able to either reduce the required time, or improve the result quality with respect to the monoprocessor version. In the latter case, in terms of Fault Coverage, the results are the best ones reported in the literature for most of the largest standard benchmark circuits. The flexibility of GATTO enables users to easily tradeoff fault coverage and CPU time to suit their needs.

The paper describes a Genetic Algorithm for the Floorplan Area Optimization problem. The algorithm is based on suitable techniques for solution encoding and evaluation function definition, effective cross-over and mutation operators, and heuristic operators which further improve the method's effectiveness. An adaptive approach automatically provides the optimal values for the activation probabilities of the operators. Experimental results show that the proposed method is competitive with the most effective ones as far as the CPU time requirements and the result accuracy is considered, but it also presents some advantages. It requires a limited amount of memory, it is not sensible to special structures which are critical for other methods, and has a complexity which grows linearly with the number of implementations. Finally, we demonstrate that the method is able to handle floorplans much larger (in terms of number of basic rectangles) than any benchmark previously considered in the literature.

The use of parallel architectures for the solution of CPU and memory critical problems in the electronic CAD area has been limited up to now by several factors, like the lack of efficient algorithms the reduced portability of the code, and the cost of the hardware. However, portable message-passing libraries are now available, and the same code runs on high-cost supercomputers, as well as on common workstation networks. The paper presents an effective ATPG system for large sequential circuits developed using the PVM library and based on a genetic algorithm. The tool, named GATTO has been run on a DEC Alpha AXP farm and on a CM-5. Experimental results are provided.

The paper deals with the problem of Floorplan Area Optimization; an approach based on Genetic Algorithms is proposed. The method produces optimal results with CPU time requirements comparable with the ones of other approaches but presents some advantages: it is simple to implement, it allows the user to easily trade off CPU time with result accuracy, it requires a limited amount of memory to store partial results, it is not sensible to special structures like nested wheels. Experimental results on the biggest problems proposed in the literature are reported.>

This paper deals with the problem of automated test pattern generation for large digital circuits. A distributed approach based on genetic algorithms is presented, which exploits the computational power of workstation networks to solve the problem even for the largest circuits. A prototypical system named GATTO is presented: the experimental results show that good results can be reached with CPU times much smaller than for previous methods, and that the distributed approach provides a good speed-up with respect to the mono-processor version. Thanks to the adoption of GAs, the method is able to dynamically adapt itself to the circuit it is applied to, and it allows the user to easily trade-off results accuracy and CPU time.>

This paper is concerned with the question of automated test pattern generation for large synchronous sequential circuits and describes an approach based on Genetic Algorithms suitable for even the largest benchmark circuits, together with a prototype system named GATTO. Its effectiveness (in terms of result quality and CPU time requirements) for circuits previously unmanageable is illustrated. The flexibility of the new approach enables users to easily trade off fault coverage and CPU time to suit their needs.