Train-to-wayside (T2W) and train-to-train (T2T) communication mode may coexist in future train-centric communication-based train control (CBTC) systems. The feasibility of train-to-train communication in urban rail transit is analyzed first. Referring to the D2D communication scenario in the general cellular network, this paper establishes a radio resource optimization model for the coexistence of train-to-train communication and train-to-wayside communication. Aiming at scheduling radio time-frequency resources in the dedicated frequency band more efficiently, we propose a Stackelberg game based radio resource management algorithm based on the consideration of different service priorities of trains. The results show that the proposed algorithm can effectively guarantee the performance of the system and improve the reliability of the CBTC system.

Accurate identification of Golgi protein types can provide useful clues to reveal the correlation between GA dysfunction and disease pathology and improve the ability to develop more effective treatments for the diseases. This paper introduces an effective and robust method to classify Golgi protein type with traditional machine learning algorithms. In which various features such as n-GDip, DCCA, psePSSM were used as training features and SVM with linear kernel was employed as a classifier. To solve the imbalance problem of the benchmark datasets, the oversampling technique SMOTE was adopted. To deal with the huge amount of features, the PCA algorithm and Fisher feature selection method were adopted to reduce feature dimensions and remove redundant features. The experimental results show that the proposed method had a further improvement compared with other traditional machine learning methods in 10-fold cross-validation, Jackknife cross-validation and independent testing, which means a further step for the clinical application of computational methods to predict the Golgi protein types.

Nowadays, in urban rail transit systems, train wayside communication system uses Wireless Local Area Network (WLAN) as wireless technologies to achieve safety‐related information exchange between trains and wayside equipment. However, according to the high speed mobility of trains and the limitations of frequency band, WLAN is unable to meet the demands of future intracity and intercity rail transit. And although the Time Division‐Long Term Evolution (TD‐LTE) technology has high performance compared with WLAN, only 20 MHz bandwidth can be used at most. Moreover, in high‐speed scenario over 300 km/h, TD‐LTE can hardly meet the future requirement as well. The equipment based on Enhanced Ultra High Throughput (EUHT) technology can achieve a better performance in high‐speed scenario compared with WLAN and TD‐LTE. Furthermore, it allows using the frequency resource flexibly based on 5.8 GHz, such as 20 MHz, 40 MHz, and 80 MHz. In this paper, we set up an EUHT wireless communication system for urban rail transit in high‐speed scenario integrated all the traffics of it. An outdoor testing environment in Beijing‐Tianjin High‐speed Railway is set up to measure the performance of integrated EUHT wireless communication system based on urban rail transit. The communication delay, handoff latency, and throughput of this system are analyzed. Extensive testing results show that the Quality of Service (QoS) of the designed integrated EUHT wireless communication system satisfies the requirements of urban rail transit system in high‐speed scenario. Moreover, compared with testing results of TD‐LTE which we got before, the maximum handoff latency of safety‐critical traffics can be decreased from 225 ms to 150 ms. The performance of throughput‐critical traffics can achieve 2‐way 2 Mbps CCTV and 1‐way 8 Mbps PIS which are much better than 2‐way 1 Mbps CCTV and 1‐way 2 Mbps PIS in TD‐LTE.

Leaky Coaxial Cables (LCXs) are widely used in tunnels and underpasses for smoother electric field coverage in wireless communication systems. But there are very few studies on LCXs working in 2.4GHz, which are the frequency bands used in 802.11b/g. The paper shows characteristics of 2.4GHz LCX through simulations and field tests. The results show that the communication through 2.4GHz frequency band LCX can provide stronger radio signals and thus better throughput compared with free space in tunnels. What's more, the handover interruption time between APs can be reduced because the Ping-Pong handover is avoided through LCX.

The paper presents a novel three-stage algorithm for very-low-light video denoising and enhancement. The proposed technique invokes twice, in the first and the third stages, the well-known Non-Local Means (NLM) method for spatial and temporal denoising: it is well adapted to the application, leading to the definition of a novel NLM tool. The intermediate stage performs a custom tone adjustment specifically aimed at enlarging the dynamic range of very dark videos. The overall approach transforms very dark videos into more watchable ones, effectively reduces very high noise, and all in all, produces high quality restored image sequences outperforming the recent state-of-the-art results. Additionally, the first and third stages can be combined as a two-step filtering scheme for normal-light videos: the novel denoising solution achieves a heavy noise removal, while reducing motion blur artifacts and preserving image details.

Power gating is a technique for efficiently reducing leakage power by disconnecting idle blocks from the power grid. When gated blocks are woken up, large amounts of switching currents are drawn in a short period of time that may introduce severe noise on the power delivery mesh. In this paper, we propose a GA-based approach to schedule power gating considering power/ground noise. We introduce a simulation-based method to accurately and efficiently estimate the worst case noise, taking all the current sources, inductance and decaps' effects into consideration. We also present an incremental scheduling procedure considering the dynamic changes of decap configuration. Experimental results show that by optimally scheduling the wake-up order under time constraints, our technique can reduce noise up to 50% compared to waking gated blocks simultaneously. The quality of results depends upon the total wake-up time constraint, locations of gated blocks, current densities of gated blocks, and decap distribution.

Power-gating is a technique for efficiently reducing leakage power by shutting off the idle blocks. However, the presence of power-gating may also introduce negative effects on power supply network, which have not been considered in the earlier design stages. Ignoring those effects may result in suboptimal power supply network designs and could potentially even nullify the intended power savings. In this paper, we analyze mutual dependencies between the sleep transistors and the P/G network, and we present a general flow to optimize the P/G supply network for power-gating. Experimental results show that sizing sleep transistor and power network separately cannot achieve optimal solution in terms of power. By compromising only 1% of the total area, our optimization method allows us to save 10% of power dissipated on decaps and sleep transistors, which is a practical solution for a power-gated system. We also report results of a study on optimal solutions for various gated areas and current densities.

In this paper, we address the problem of estimating clock-skew bounds in presence of power supply and process variations. We present a novel technique based on sequence of linear programs to compute the upper and lower bounds of clock skew. We apply our method to pairs of sinks between which logic paths in the circuit exist. When spatial correlations of process variations are known, our method provides more accurate results which reflect the real design. We use accurate models and time-domain analysis ts calculate the clock network delay and delay sensitivity. The experimental results demonstrate that our technique is capable of providing very accurate skew bounds estimation (within 10% error as compared to Monte-Carlo method) in acceptable run-times.

Power-gating is a technique for saving leakage power by shutting off the idle blocks. However, without good understanding and careful design, negative effects of power gating may overwhelm the potential gain and may make the technique not worth the effort. In this paper, we report on our study of the benefits and costs of the power-gating technique in terms of power, area, and performance. We model and analyze several strongly related parameters such as sleep-transistor size, decap area, and supply voltage level. We also report on our experiments to demonstrate how the gated area, circuit behavior and power mesh granularity affect the power gating technique at the system level. Experimental results show that, by compromising 4% of the total area and 5% of the dynamic power, we can achieve 47% leakage power saving while maintaining the same performance. With technology scaling down, the saving is significant. We conclude that we can benefit from the power-gating technique in future technology nodes.

We investigate the problem of clock network sizing subject to general skew constraints. A novel approach based on sequential linear programming is presented. The original nonlinear programming problem is transformed into a sequence of linear programs by taking the first-order Taylor's expansion of clock path delay with respect to buffer and/or wire widths. For each linear program, the sensitivities of clock path delay, with respect to buffer and/or wire widths, are efficiently updated by applying time-domain analysis to the clock network in a divide-and-conquer fashion. Our technique can take into account power supply and process variations. We demonstrate experimentally that the proposed technique is not only capable of optimizing effectively the skew and area of clock network, but also of providing more accurate delay and skew results compared to the traditional approaches.

In this paper we present the Gain-based Logic Block Array (GLA), a new via-programmable regular fabric. GLA is an array of Gain-based Logic Blocks (GLBs). The GLB is a semi-universal logic block designed based on logical effort theory[12]. Customization of the GLBs is provided by programmable vias. To achieve the best performance, appropriate fabric has to be selected from a family of GLAs with different performance-area trade-offs. We describe a synthesis and placement flow which, for a given design to be implemented, allows us to select the best GLA from the candidate family.