Demo Data from EDBT 2026 / reviewers in the wild / expert
Dongning Liang
dblp:35/3678
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2001
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 56% Electronic design automation · 44% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › timing prediction
critical path prediction |
0.0 | 1 | 2001 | Dynamic Prediction of Critical Path Instructions · HPCA 2001 |
Processor architecture and microarchitecture
value prediction |
0.0 | 1 | 2001 | Dynamic Prediction of Critical Path Instructions · HPCA 2001 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0dynamic instruction analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2001 | Dynamic Prediction of Critical Path InstructionsabstractModern processors come close to executing as fast as role dependences allow. The particular dependences that constrain execution speed constitute the critical path of execution. To optimize the performance of the processor we either have to reduce the critical path or execute it more efficiently. In both cases, it can be done more effectively if we know the actual instructions that constitute that path. This paper describes critical path prediction for dynamically identifying instructions likely to be on the critical path, allowing various processor optimizations to take advantage of this information. We show several possible critical path prediction techniques and apply critical path prediction to value prediction and clustered architecture scheduling. We show that critical path prediction has the potential to increase the effectiveness of these hardware optimizations by as much as 70%, without adding greatly to their cost. Eric Tune, Dongning Liang, Dean M. Tullsen, Brad Calder |
HPCA | 2 |