Fully distributed memory multi-processor systems-on-chip MPSoCs implemented in a multi-tiled architecture provide promising platforms to support parallel data-flow application. Tiles are connected by network-on-chip NoC, each contains a core with necessary peripherals and a communication device. Such systems are susceptible to reliability issues like thermal spots. Task migration still provides an effective system-level solution for such issues. An agent based task migration solution is designed to target tiled MPSoCs. These agents are responsible for executing migration. In order to execute task migration, a middleware1 layer is developed to provide necessary services used by the agents. Also, Agents use information about both application(s) task graph and application(s) mapping on different tiles so as to be able to control right tasks. Since number of tiles is continuously increasing thanks to advancements in transistor scaling technology, automatic software generation tool-chain is no longer optional. In this work, we expand a software automatic generation tool-chain and a task migration solution, all designed for tiled MPSoCs. We emphasize on how this task migration solution is integrated in this software tool-chain so that generated software is equipped with task migration capability transparently from application developers. We show how agents are placed with applications and how necessary information for such agents are generated and linked with them. The tool-chain is capable of generating code for ARM based simulation and x86 real hardware platforms. We show experimental results of task migration memory and performance overheads.

EURETILE investigates foundational innovations in the design of massively parallel tiled computing systems by introducing a novel parallel programming paradigm and a multi-tile hardware architecture. Each tile includes multiple general-purpose processors, specialized accelerators, and a fault-tolerant distributed network processor, which connects the tile to the inter-tile communication network. This paper focuses on the EURETILE software design flow, which provides a novel programming environment to map multiple dynamic applications onto a many-tile architecture. The elaborated high-level programming model specifies each application as a network of autonomous processes, enabling the automatic generation and optimization of the architecture-specific implementation. Behavioral and architectural dynamism is handled by a hierarchically organized runtime-manager running on top of a lightweight operating system. To evaluate, debug, and profile the generated binaries, a scalable many-tile simulator has been developed. High system dependability is achieved by combining hardware-based fault awareness strategies with software-based fault reactivity strategies. We demonstrate the capability of the design flow to exploit the parallelism of many-tile architectures with various embedded and high performance computing benchmarks targeting the virtual EURETILE platform with up to 192 tiles.

With such ongoing sophistication in embedded applications, higher computational powers are becoming more required. As a result, a wide transition to multi-processor system on chip has been adopted. Our study focuses on fully distributed memory MPSoC which is implemented in multi-tiled architecture. A tile contains at least one processor and associated peripherals with a distributed network processor which is responsible for inter-tile communications. All tiles are connected in a 3D torus network. In this paper, we present a solution for a lightweight task migration on such architectures. It is based on wise task code replication in statically chosen locations (tiles). It provides the system with the ablility to remap its tasks at runtime. This work emphasizes on solving all issues arising from communication inconsistency shedding the light on implementation details. Experiments show the effectiveness of the approach, and detail performances and limitations. The solution has been implemented on a multi-tiled virtual ARM-CortexA9 based platform with an embedded operating system.

We introduce a static binary translation flow in native simulation context for cross-compiled VLIW executables. This approach is interesting in situations where either the source code is not available or the target platform is not supported by any retargetable compilation framework, which is usually the case for VLIW processors. The generated simulators execute on a Hardware-Assisted Virtualization (HAV) based native platform. We have implemented this approach for a TI C6x series processor and our simulation results show a speed-up of around two orders of magnitude compared to the cycle accurate simulators.

Fast Instruction Set Simulators (ISS) are a critical part of MPSoC design flows. The complexity of developing these ISS combined with the ability to extend instruction sets tend to make automated generation of ISS a need. One important part of every ISS is its instruction decoder, but as the encoding of instruction sets becomes less orthogonal because of the incremental addition of instructions, the generation of a decoder is not anymore an obvious task. In this paper, we present two automated decoder generation strategies that are able to handle non-orthogonal instruction encodings. The first one builds a decision tree that does not consider the instruction's occurrences while the second considers these frequencies. In both cases, we use binary decision diagrams to represent the instructions encodings and the complex conditions due to the non-orthogonality of the encodings in order to generate the decoders. Our experiments on the MIPS and ARM (including VFP and Neon extensions) instruction sets show that both algorithms produce efficient decoders, and that it is beneficial to consider instruction frequencies.

This paper presents a strategy to speed-up the simulation of processors having SIMD extensions using dynamic binary translation. The idea is simple: benefit from the SIMD instructions of the host processor that is running the simulation. The realization is unfortunately not easy, as the nature of all but the simplest SIMD instructions is very different from a manufacturer to an other. To solve this issue, we propose an approach based on a simple 3-addresses intermediate SIMD instruction set on which and from which mapping most existing instructions at translation time is easy. To still support complex instructions, we use a form of threaded code. We detail our generic solution and demonstrate its applicability and effectiveness using a parametrized synthetic benchmark making use of the ARMv7 NEON extensions executed on a Pentium with MMX/SSE extensions.

Symmetric multiprocessor architectures (SMP) are gaining popularity for system on chip (SoC) applications as they provide an interesting power/performance/flexibility tradeoff. We address the problem of power consumption in such architectures by designing a new adaptive Dynamic Voltage Frequency Scaling (DVFS) algorithm for non real time operating system (non-RTOS) running on a SMP-SoC. We show the effectiveness of our algorithm on a cycle accurate simulation environment running a real-life multi-threaded application. The experimental results show a potential gain of up to 55%.

We present Worldsens,a prototyping and development work for wireless sensor protocols and applications.Our relies on two simulators,WSim and WSNet, and proposes a full simulation and performance estimation embedded platforms with instruction and radio byte curacy.During this demo,we propose to demonstrate the interest of the two simulators in stand-alone and in cooperative use.

This paper presents a performance and energy consumption simulator for deeply embedded hardware platforms such as sensor network nodes. These tools are based on cycle accurate simulation of complete hardware platforms executing the real application code. This allows designers to get fast performance and consumption estimations without deploying software on target hardware, while being independent of any compilation tools or software components such as network protocols or operating systems.