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Ram Kumar 0001

dblp:35/4304-1 · DBLP profile ↗
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5ranked-venue papers
2as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 4 · 1 first-authorSystems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Systems and software security · 100%
Computer architecture, parallel and distributed computing, and storage systems
3 papers
Embedded and real-time systems · 65% Memory systems · 35%
Software engineering, system software, and programming languages
2 papers
Operating systems · 100%
Computer networks
2 papers
Internet of things and sensor networks · 93% Wireless networking · 7%

Topics — the 15 heaviest of 17, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Systems and software security
memory safety
0.122007
Harbor: software-based memory protection for sensor nodes · IPSN 2007
A System For Coarse Grained Memory Protection In Tiny Embedded Processors · DAC 2007
Systems and software security
memory protection
0.112007
A System For Coarse Grained Memory Protection In Tiny Embedded Processors · DAC 2007
Systems and software security › isolation
software fault isolation
0.112007
Harbor: software-based memory protection for sensor nodes · IPSN 2007
Operating systems › resource management › memory management
memory protection
0.112007
Harbor: software-based memory protection for sensor nodes · IPSN 2007
Operating systems › system security › operating system security › protection mechanism › isolation
sandboxing
0.112007
Harbor: software-based memory protection for sensor nodes · IPSN 2007
Embedded and real-time systems
embedded processor
0.112007
A System For Coarse Grained Memory Protection In Tiny Embedded Processors · DAC 2007
Memory systems
memory protection
0.112007
A System For Coarse Grained Memory Protection In Tiny Embedded Processors · DAC 2007
Internet of things and sensor networks
wireless sensor network
0.122005
Timing-sync protocol for sensor networks · SenSys 2003
A dynamic operating system for sensor nodes · MobiSys 2005
Internet of things and sensor networks › time synchronization
network-wide synchronization
0.012003
Timing-sync protocol for sensor networks · SenSys 2003
Internet of things and sensor networks
time synchronization
0.012003
Timing-sync protocol for sensor networks · SenSys 2003
Embedded and real-time systems › embedded software engineering › embedded software development
microcontroller deployment
0.012007
A System For Coarse Grained Memory Protection In Tiny Embedded Processors · DAC 2007
Embedded and real-time systems › embedded software › embedded operating systems
sensor node operating system
0.012007
Harbor: software-based memory protection for sensor nodes · IPSN 2007
Internet of things and sensor networks › low-power wireless
mote-class sensor node
0.012005
A dynamic operating system for sensor nodes · MobiSys 2005
Embedded and real-time systems › wireless communication › wireless sensor networks
wireless sensor node
0.012005
A dynamic operating system for sensor nodes · MobiSys 2005
Wireless networking › wireless mesh network
multihop wireless network
0.012003
Timing-sync protocol for sensor networks · SenSys 2003

Methods — techniques the papers use, named apart from their topics

control-flow integrity · 0.2binary rewriting · 0.2watchdog timer · 0.2dynamic loading · 0.2cooperative scheduling · 0.2safe stack · 0.1jump table · 0.1hardware accelerators · 0.1hierarchical pairwise synchronization · 0.0
YearPublicationVenuePosition
2007 A System For Coarse Grained Memory Protection In Tiny Embedded Processors
abstract
Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no form of memory protection. Programming errors in one application can easily corrupt the state of the operating system and other applications on the microcontroller. In this paper we propose a system that provides memory protection in tiny embedded processors. Our system consists of a software run-time working with minimal low-cost architectural extensions to the processor core that prevents corruption of state by buggy applications. We restrict memory accesses and control flow of applications to protection domains within the address space. The software run-time consists of a Memory map: a flexible and efficient data structure that records ownership and layout information of the entire address space. Memory map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system. We preserve control flow integrity by maintaining a Safe stack that stores return addresses in a protected memory region. Cross domain function calls are redirected through a software based jump table. Enhancements to the microcontroller call and return instructions use the jump table to track the current active domain. We have implemented our scheme on a VHDL model of ATMEGA103 microcontroller. Our evaluations show that embedded applications can enjoy the benefits of memory protection with minimal impact on performance and a modest increase in the area of the microcontroller.
Ram Kumar 0001, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava 0001
DAC1
2007 Harbor: software-based memory protection for sensor nodes
abstract
Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no form of hardware memory protection. Programming errors in one application can easily corrupt the state of the operating system or other applications. In this paper, we propose Harbor, a memory protection system that prevents many forms of memory corruption. We use software based fault isolation ("sandboxing") to restrict application memory accesses and control flow to protection domains within the address space. A flexible and efficient memory map data structure records ownership and layout information for memory regions; writes are validated using the memory map. Control flow integrity is preserved by maintaining a safe stack that stores return addresses in a protected memory region. Run-time checks validate computed control flow instructions. Cross domain calls perform low-overhead control transfers between domains. Checks are introduced by rewriting an application's compiled binary. The sand-boxed result is verified on the sensor node before it is admitted for execution. Harbor's fault isolation properties depend only on the correctness of this verifier and the Harbor runtime. We have implemented and tested Harbor on the SOS operating system. Harbor detected and prevented memory corruption caused by programming errors in application modules that had been in use for several months. Harbor's overhead, though high, is less than that of application-specific virtual machines, and reasonable for typical sensor workloads.
Ram Kumar 0001, Eddie Kohler, Mani Srivastava 0001
IPSN1
2005 A dynamic operating system for sensor nodes
abstract
Sensor network nodes exhibit characteristics of both embedded systems and general-purpose systems. They must use little energy and be robust to environmental conditions, while also providing common services that make it easy to write applications. In TinyOS, the current state of the art in sensor node operating systems, reusable components implement common services, but each node runs a single statically-linked system image, making it hard to run multiple applications or incrementally update applications. We present SOS, a new operating system for mote-class sensor nodes that takes a more dynamic point on the design spectrum. SOS consists of dynamically-loaded modules and a common kernel, which implements messaging, dynamic memory, and module loading and unloading, among other services. Modules are not processes: they are scheduled cooperatively and there is no memory protection. Nevertheless, the system protects against common module bugs using techniques such as typed entry points, watchdog timers, and primitive resource garbage collection. Individual modules can be added and removed with minimal system interruption. We describe SOS's design and implementation, discuss tradeoffs, and compare it with TinyOS and with the Maté virtual machine. Our evaluation shows that despite the dynamic nature of SOS and its higher-level kernel interface, its long term total usage nearly identical to that of systems such as Matè and TinyOS.
Chih-Chieh Han, Ram Kumar 0001, Roy Shea, Eddie Kohler, Mani Srivastava 0001
MobiSys2
2005 Computation Hierarchy for In-Network Processing
Vlasios Tsiatsis, Ram Kumar 0001, Mani Srivastava 0001
Mob. Networks Appl.2
2003 Timing-sync protocol for sensor networks
abstract
Wireless ad-hoc sensor networks have emerged as an interesting and important research area in the last few years. The applications envisioned for such networks require collaborative execution of a distributed task amongst a large set of sensor nodes. This is realized by exchanging messages that are time-stamped using the local clocks on the nodes. Therefore, time synchronization becomes an indispensable piece of infrastructure in such systems. For years, protocols such as NTP have kept the clocks of networked systems in perfect synchrony. However, this new class of networks has a large density of nodes and very limited energy resource at every node; this leads to scalability requirements while limiting the resources that can be used to achieve them. A new approach to time synchronization is needed for sensor networks.In this paper, we present Timing-sync Protocol for Sensor Networks (TPSN) that aims at providing network-wide time synchronization in a sensor network. The algorithm works in two steps. In the first step, a hierarchical structure is established in the network and then a pair wise synchronization is performed along the edges of this structure to establish a global timescale throughout the network. Eventually all nodes in the network synchronize their clocks to a reference node. We implement our algorithm on Berkeley motes and show that it can synchronize a pair of neighboring motes to an average accuracy of less than 20ms. We argue that TPSN roughly gives a 2x better performance as compared to Reference Broadcast Synchronization (RBS) and verify this by implementing RBS on motes. We also show the performance of TPSN over small multihop networks of motes and use simulations to verify its accuracy over large-scale networks. We show that the synchronization accuracy does not degrade significantly with the increase in number of nodes being deployed, making TPSN completely scalable.
Saurabh Ganeriwal, Ram Kumar 0001, Mani Srivastava 0001
SenSys2