A parallel non-Monte Carlo transient noise analysis method for efficient general nonlinear analysis is presented. The proposed method extends a previous method to include flicker noise. The implementation of the proposed method in a SPICE-like circuit simulator is described. Additional practical considerations are discussed. Higher parallel efficiency is achieved by balancing the parallel loads. The optimal number of processors is automatically selected as part of load balancing. A new time domain flicker noise circuit representation that increases the computational efficiency of the proposed method and the underlying serial method is presented. Three examples of transient noise analysis are provided: a low-noise amplifier circuit, a mixer circuit, and a distributed amplifier circuit.

Recently, Polynomial Chaos (PC) has been proposed as efficient approach for performing uncertainty quantification in the the context of electronic design automation. A related approach, Rational Polynomial Chaos (RPC) was later developed for applications that exhibit a large variation in the quantity of interest. One of the key bottlenecks for both PC and RPC is the number of circuit evaluation needed, particularly as the number of random parameters increases (often referred to as the curse of dimentionality). In this paper, we propose an approach that uses sensitivity information to significantly reduce the number of circuit evaluations needed for Rational Polynomial Chaos. Numerical examples are given to illustrate the accuracy and efficiency of the proposed approach.

Measuring the effects of nonlinear intermodulation distortion is one of the main requirements in the design of radio frequency circuits. The third-order intercept point (IP3) is one of the main figures of merit that is used to characterize this distortion and is expensive to compute due to the presence of multi-tone inputs. Recently, an efficient method for computing the third order intercept point, using moments analysis, was presented. However, this approach does not provide any sensitivity information. In this paper, we propose an efficient and robust method for computing the sensitivity of IP3 using adjoint moments with minimal additional computational cost.

Obtaining the value of the third order intercept point using traditional simulation techniques typically requires a nonlinear steady state analysis with multitone inputs, which is very computationally expensive. In this paper, a new method is presented for the computation of the third order intercept point. Using the proposed approach, the necessary Volterra kernels are computed directly from the harmonic balance equations. The only computation cost is that of solving a set of sparse linear equations. Furthermore, only one input tone is required in this case, which greatly reduces the size of the equations and thus the computation cost.

Intermodulation distortion is one of the key design requirements of Radio Frequency circuits. The standard approach for analyzing distortion using circuit simulators is to mimic measurement environments and compute the response due to a two-tone input. This considerably increases the CPU cost of the simulation because of the large number of variables resulting from the harmonics of these two tones and their intermodulation products. In this paper, we propose an analytical method for directly obtaining the intermodulation distortion from the Harmonic Balance equations with a only single-tone input, without the need to perform a Harmonic Balance simulation. The proposed method is shown to be significantly faster than traditional simulation based approaches.

Nonlinear distortion, typically defined using the third order intercept point (IP3), is one of the key figures of merit that are critical in the design of RF communication circuits. The calculation of IP3 is typically based on analytical approaches such as Volterra series which are very complex and difficult to apply to circuits of arbitrary complexity, or on simulation based methods which require multi-tone inputs and thus result in a very high CPU cost. In this paper a new method based on the computation of the circuit moments is proposed. The new approach uses the circuit moments in order to numerically compute the Volterra kernels. This automates the process of numerically obtaining such kernels for any circuit and results in an efficient approach for the computation of IP3

In recent years, congruence transformation based model order reduction methods have proven to be an effective tool in dealing with increasing computational complexities which arise from the simulation of interconnect networks. However, most existing model order reduction methods are only efficient in coping with systems with small number of ports. Moreover, model order reduction methods based on Krylov subspace result in a macromodel which is not optimal. In this paper, a two-level reduction method is proposed to address the above two limitations. In the first level reduction, prior information about the types the loads that can be connected to the ports and their ranges of values is exploited to obtain a reduced macromodel whose size is not very sensitive to the number of ports. Since the first level reduction uses congruence transformation based on Krylov subspace techniques, which contain redundant information. This leads to a second level reduction using singular value decomposition. The proposed method is shown to produce a macromodel which is significantly smaller than standard methods.

Model order reduction (MOR) has proven to be an effective tool in combatting the computational complexities that arise from the simulation of large interconnect networks. Furthermore, parametric model order reduction (PMR) was recently developed for extending this concept to optimization and design space exploration of interconnect networks. The difficulty with current PMR methods is that the reduced macromodel is dense which reduces the efficiency of the simulation. In this paper a new formulation is proposed which allows for the sparsification of the reduced parametric macromodel, thus resulting in significant CPU cost saving as is demonstrated in the examples.

This paper presents a new algorithm for computing the sensitivity of steady-state responses of nonlinear circuits with respect to an arbitrary network parameter. The proposed algorithm is based on circuit-reduction techniques obtained through nonlinear-projection approaches. The main idea in the proposed sensitivity-computation algorithm is based on projecting the adjoint system of equations onto a subspace of smaller dimension. Continuation methods are then applied on the reduced system to trace the solution trajectory of the adjoint system in the reduced space. We show that once the steady-state solution has been obtained using nonlinear order reduction, the computational cost required to compute sensitivity is only a limited number of forward/backward substitutions. Numerical examples are presented to demonstrate the accuracy and efficiency of the proposed algorithm.

This paper describes a systematic algorithm for obtaining passive time domain reduced order transmission line macromodels. The proposed algorithm makes use of a new order reduction technique that removes the redundant poles obtained using conventional order reduction methods. The reduced macromodel is passive by construction.