Symbolic processing is distinguished from other types of computation, e.g. numeric, commercial, or real-time, by the fact that its metadata is both complex and complicated. That is, the data objects manipulated by symbolic programs have descriptions which are not simple and not always predictable. The metadata is complex in the sense that the data objects are multi-faceted, having a variety of attributes and relationships to other objects. Processing this multidimensional data is done in slices, involving just a few types of attributes at a time, so different programs must deal with different projections (or views) of the data. The metadata is complicated in that it is recursive, meaning that the interpretation of a data object requires processing other instances of the same object class, to an unpredictable extent. Thus complexity and complication in metadata translate directly into data management and resource (space and time) management problems in processing.

This paper explores the use of a proposed programmable storage/logic array (SLA) chip as a general purpose universal logic element for digital computers. The SLA is compared to other programmable logic arrays in implementation and utilization, showing how it permits construction of complete digital subsystems on one chip without sacrifice in programmability. When compared with other contending very large-scale integrated technology (VLSI) approaches, such as microprogrammed processors and gate arrays, the SLA offers an attractive combination of cost, performance, and ease of implementation.

We explore the use of a proposed general purpose programmable Storage/Logic Array chip (SLA) as a universal logic element for digital computers. Design examples are given to show how SLAs could be used in computer design. This approach to VLSI is compared and contrasted with other contending approaches using microprocessors, gate arrays and customized VLSI chips. The SLA appears attractive because of low cost, reasonable high performance and shorter implementation time.

This paper presents an analytical study of speed-cost tradeoffs in memory hierarchy design. It develops an optimization criterion by which average access time, i. e., memory system delay, is minimized under a cost constraint for a hierarchy with given memory sizes and access probabilities. Using a power function assumption relating speed and cost of memory units, it is shown that an optimized hierarchy has the property of balanced cost and delay distributions, in that each memory unit makes the same percentage contribution to memory system cost as it makes to average system access delay. Using the same assumption, a lower bound on average access time is developed, showing that access time is roughly related to a cube-root averaging of access probabilities. These results provide useful tools for developing memory hierarchy design strategies and for evaluating data placement algorithms.

A computer architecture is proposed which uses a hardware implemented descriptor system to provide facilities for explicit data typing, memory relocation, and access protection at the data element level. The problem of having to fetch descriptors for every operand access is overcome by storing descriptors in small fast memories of various types. The resulting machine runs simple languages (such as FORTRAN) as fast as conventional architectures, and offers significant speed improvement for languages using complex data types (such as data management systems). The cost of the descriptor storage hardware is shown to be modest, so this architecture would be suitable for machines as small as a large minicomputer.

This note indicates some difficulties in applying the above paper's1computational "work measure."