This paper proposes a four-level pulse amplitude modulation (PAM-4) half-rate receiver, incorporating a current-reuse analog front-end (AFE) and a single-loop half-rate reference-less bang-bang clock and data recovery (BBCDR) in a 40-nm CMOS process. The inverter-based AFE is introduced to compensate for the channel insertion loss efficiently, utilizing a continuous-time linear equalizer (CTLE) that works in conjunction with feed-forward mid-frequency equalization and a variable gain amplifier (VGA) that employs a complementary-Gilbert gm-cell for enhanced current efficiency. The gm-transimpedance-amplifier (Gm-TIA) topology is employed in the AFE to extend the gain-bandwidth (GBW) product. To overcome the design challenges of high-speed clock generation and distribution, the BBCDR adopts a half-rate architecture. Two asymmetric locking points (LPs) are adopted for the bang-bang phase detector (BBPD) by the clock-phase-selection (CPS) scheme and the hybrid control circuit (HCC) is adopted to automate the frequency acquisition. To eliminate the impact of the middle transition of the PAM-4 signal and enhance the jitter performance of the proposed PAM-4 receiver, the pattern-selection technique is adopted in the proposed pattern-based BBPD (PB-BBPD). The measurement results demonstrate that the receiver can compensate for −8.5 dB channel loss at 12.5 GHz and automatically eliminate the frequency errors with the single-loop architecture. Moreover, by incorporating the proposed PB-BBPD, the PAM-4 receiver achieves an improved jitter performance with a power efficiency of 2.47 pJ/bit.

This paper presents a$2\times 80$Gb/s single-ended trans-admittance trans-impedance (TAS-TIS) 4-level pulse amplitude modulation (PAM-4) receiver with crosstalk cancellation and signal reutilization technique in 28-nm CMOS. Based on the TAS-TIS architecture, to achieve a precise cancellation of the far-end crosstalk, a common mode gain rejection methodology is proposed in the balanced differentiator, ensuring low gain mismatch and low phase skew. Moreover, the proposed Gm-doubler technique in the TAS-TIS architecture enhances the gain of the adder under limited supply voltage conditions. By employing the series peaking combined with an active inductor in the adder, the bandwidth of adder is improved by a factor of 2.2, and the group delay variation is effectively optimized by 65%. The proposed current-mirror-based continuous-time linear equalizer (CTLE) provides high-frequency and low-frequency compensation with 25% power saving. Overall, the measurement results of the proposed receiver demonstrate$2\times 80$Gb/s PAM-4 eyes with an efficiency of 0.83 pJ/bit/lane and$2\times 56$Gb/s non-return-to zero (NRZ) eyes over a pair of PCB traces with 13 dB loss at 20 GHz and 28 dB loss at 28 GHz, respectively.

A 112-Gb/s single-ended (SE) four-level pulse amplitude modulation (PAM-4) transceiver front-end for the reach-extension module in long-reach (LR) link is proposed. The receiver front-end features an SE-to-differential (S2D) amplifier and a continuous-time linear equalizer (CTLE). Asymmetric inductive peaking, compensation capacitance, and current blending techniques are employed in S2D to eliminate the mismatch at the pseudo-differential outputs. A compact and peaking-enhanced CTLE is achieved by the inductor reused technique. The transmitter front-end is based on a differential-to-SE (D2S) driver where the negative capacitance technique is proposed to extend its bandwidth. Fabricated in 130-nm SiGe BiCMOS technology, our SE transceiver front-end demonstrates a data rate of 112-Gb/s PAM-4 at a 20-dB channel loss with an FoM of 0.09 pJ/bit/dB and BER of$3.21e$-4.

This paper presents a type-II sampling phase-locked loop (SPLL) that accelerates the locking process by exploiting a time-to-digital converter (TDC) based automatic frequency and phase calibration (AFPC) technique. The proposed AFPC accelerates the frequency acquisition by using a type-I loop to map the quantized phase error to the switched-capacitor (SC) control word of the voltage-controlled oscillator (VCO). The subsequent phase error after frequency locking is swiftly reduced within one TDC resolution by adjusting the division ratio of the multi-modulus divider (MMD) with little hardware expenditure. The proposed AFPC can guarantee a fast-locking time at different initial frequencies, which is insensitive to the variation of TDC resolution. This paper also contributes to a design strategy for the AFPC loop, e.g., the required frequency step of the SC and the TDC resolution, based on the analysis of the lock-in range of the SPLL. Fabricated in 28-nm CMOS with a core area of 0.15 mm$^{\mathbf {2}}$, the 6.0-to-6.9GHz SPLL prototype using a reference (REF) clock of 100 MHz achieves a locking time of$0.62~\mu $s ($62{T} _{\mathbf {REF}}$) at an 880-MHz hopping frequency. At 6.5 GHz, the SPLL consumes 4.6 mW and measures an RMS jitter and REF spur of 99 fs and –71.6 dBc, respectively, corresponding to a jitter figure-of-merit (FoM$_{\mathbf {jitter}}$) of –253.5 dB.

This paper presents signal integrity augmentation design techniques in a 64-GBaud transimpedance amplifier (TIA) for coherent optical communication. In the FE-TIA, a bonding wire ringing reduction technique and an input DC current cancellation (IDCC) loop adapted for coherent communication are proposed. In the post amplifiers, a group delay variation (GDV) friendly bandwidth boosting technique is proposed to achieve optimal time domain performance. A non-linearity cancellation technique and a high-linearity gain control approach are proposed in both circuit and system levels. These signal integrity augmentation techniques form a toolkit to solve the design challenges in bandwidth, linearity, GDV, ringing, offset, crosstalk, etc. in high-speed high-order modulation communication. Fabricated in a 90-nm SiGe BiCMOS technology, the TIA shows input-referred noise current density of 15.1 pA/$\surd $Hz, bandwidth of over 40 GHz with GDV less than ±3.75 ps. The TIA gain can be adjusted between$150~\Omega $- 5 K$\Omega $, which enables maximum overload input current of 3 mApp. The total harmonic distortion (THD) is less than 3% and the crosstalk between two channels is less than -3 dB. The chip consumes 264 mW from 3.3 V supply.

This paper presents a fully-integrated flipped-voltage-follower-based low-dropout regulator (LDO), with proposed high-gain two-stage cross-coupled error amplifier (XCEA). Besides, the effectiveness of bypass capacitors and diversified load capacitors is discussed. Consuming$\mathbf{170}-\boldsymbol{\mu} \mathbf{A}$quiescent current and occupying area of 0.019 mm2, the LDO features 25-MHz unity-gain bandwidth (UGB) at 20-mA load to satisfy fast response requirement in high-speed transmitter. The simulated voltage undershoot is 38.85 mV for a load transient current stepping from$\mathbf{1}\ \boldsymbol{\mu} \mathbf{A}$to 25 mA in 50 ps with$\boldsymbol{C}_{\mathbf{L}} =\mathbf{100}\ \mathbf{pF}$. Owing to the proposed XCEA and the filter capacitor, the PSR is measured to be -41 dB at 100 kHz and -36 dB at 1 MHz.

This paper presents a low power injection-locked oscillator (ILO)-type clock and data recovery (CDR) in 40 nm CMOS. An efficient “phase reset” scheme is proposed to periodically realign the clock phase to the rising edge of data. The frequency information is extracted by comparing the rising edge of the data and the clock after aligning the phase using a bang-bang phase detector (BBPD). Additionally, a low power injection-locked two-stage ring digitally controlled oscillator (ILDCO) is employed to provide four-phase quadrature clock and significantly reduce the power consumption. Based on the proposed architecture, the fabricated CDR consumes only 5.8 mW from a 0.9 V supply, while being able to extract the clock signal from 6.15 to 10.9 Gb/s input data with a measured jitter tolerance (JTOL) of 0.15 UIpp at the highest frequency, indicating that the CDR meets the OC-192 mask. Furthermore, the proposed CDR demonstrates a substantial improvement in the power efficiency of 0.58 pJ/bit.

A Power-area-efficient output-capacitorless low- dropout (OCL-LDO) regulator with fast transient response is presented in this paper. The proposed technique permits the regulator to achieve small undershoot (overshoot) when the load steps up (down) and consumes little extra power. The proposed LDO regulator has been implemented and fabricated in a 0.18- μm CMOS process. It occupies an active area of0.0071mm2. The simulated results have shown that the proposed circuit consumes a quiescent current of 0.7 μ at no load, regulating the output at 0.7 V from a voltage supply of 0.9 V. The simulated transient output voltage is 47 mV when load current is stepped from 1 mA to 20 mA in 400 ns with Cl=3D10 pF. Meanwhile, this circuit shows a good of flgure-of-merit (FOM).

This article presents a$4 \times 10$Gb/s low-noise adaptive optical receiver, utilizing a current-reuse architecture and channel crosstalk-remove techniques in 65-nm CMOS process. The receiver integrates a transimpedance amplifier (TIA), a continuous-time linear equalizer (EQ), high-gain and high-bandwidth limiting amplifiers, and a 50-$\Omega $output driver into a single die. The TIA employs a common-source-based pseudo-differential topology with input series inductive peaking and$g_{m}$-enhancement to improve bandwidth and noise performance. An automatic-gain-control loop scheme is presented which solves the bandwidth variation issue caused by variation of the TIA input impedance, across a large dynamic range of a small input to a maximum overload current. Multiple crosstalk reduction techniques are adopted to improve the channel isolation performance. The 850-nm vertical cavity surface emitting laser (VCSEL)-based full-link measurement results show that the optical receiver achieves$20.4~\mu \text{A}_{\mathrm {pp}}$sensitivity bit-error-rate (BER$ < 1\text{e}$-12) with a 200-fF photodiode, competitive with other prior CMOS-based TIAs. The crosstalk over different channels is also measured, demonstrating only a sensitivity penalty of 1 dB.

In this paper, we present a linear optical receiver for 112-Gb/s PAM-4 optical link. We propose a transimpedance front-end that optimizes thermal noise, power supply noise rejection, linearity and bandwidth altogether. The pseudo-differential structure is employed to achieve both low thermal noise and good power supply noise rejection. A transimpedance amplifier (TIA) gain control technique is proposed to improve linearity at both topology and transistor level while maintaining stability. An NIC-CTLE combo extends bandwidth with optimized frequency response. Designed in a 130nm SiGe BiCMOS process, the receiver realizes 37 GHz total bandwidth and input-referred noise of 19.8 pA/√Hz. The transimpedance gain can vary from 70 dB Ω to 50 dBΩ, which enables maximum input overload current of 1.8 mApp with <; 5% THD at differential output swing of 600 mVpp. The receiver consumes 77mA from 3.3V supply.

This article presents a low-power 1/4-rate four-level pulse amplitude modulation (PAM4) receiver with an adaptive variable-gain rectifier (AVGR)-based decoder in 28-nm CMOS technology. The PAM4 input signal is preconditioned by a continuous-time linear equalizer (CTLE) then sampled into four branches of decoders by 1/4-rate clocks. The proposed AVGR-based PAM4-to-nonreturn-to-zero (NRZ) decoder performs gain adaptation and amplitude rectification simultaneously for decoding the least significant bit (LSB). The linear sense amplifier in the AVGR is modified from a latch to achieve a high gain and low power. Compared with the full-rate receiver adopting a decoder consisting of three comparators, this design achieves a better power efficiency by employing a 1/4-rate topology and merging a variable-gain function into the decoder. Experimental results demonstrate that the receiver chip can receive and decode a 24-Gb/s 190-mVppPAM4 signal at a BER of 10-11and a bit efficiency of 1.38 pJ/bit.