In Breast Conserving Therapy, surgeons measure the thickness of healthy tissue surrounding an excised tumor (surgical margin) via post-operative histological or visual assessment tests that, for lack of enough standardization and reliability, have recurrence rates in the order of 33%. Spectroscopic interrogation of these margins is possible during surgery, but algorithms are needed for parametric or dimension reduction processing. One methodology for tumor discrimination based on dimensionality reduction and nonparametric estimation-in particular, Directional Kernel Density Estimation-is proposed and tested on spectral image data from breast samples. Once a hyperspectral image of the tumor has been captured, a surgeon assists by establishing Regions of Interest where tissues are qualitatively differentiable. After proper normalization, Directional KDE is used to estimate the likelihood of every pixel in the image belonging to each specified tissue class. This information is enough to yield, in almost real time and with 98% accuracy, results that coincide with those provided by histological H&E validation performed after the surgery.

It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often the case that by the end of a design project, multiple C models exist for different uses. Clearly, this leads to wasted effort on the part of model developers, and creates risk of functional divergence across models. In this paper we present some guidelines for system-level modeling and RTL design to allow for efficiently leveraging the system-level model for RTL verification via simulation based techniques, as well as via sequential equivalence checking. The paper presents the challenges of keeping system-level models and RTL synchronized from a functional perspective and presents some techniques for overcoming these challenges.

It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). These models are written in C++ primarily because it is possible to achieve very high simulation speeds, but also because it is productive to code at high levels of abstraction. In this paper we present a modeling methodology that continues to exploit the inherent advantages of writing models in C++ while ensuring that they are usable for formal verification of RTL through the use of sequential equivalence checking technology. An industrial case study is presented to show the validity of the approach.