We are facing major technological, cost & complexity challenges. Today, I believe we understand the drivers and emerging challenges - but I don't think we've grasped how these changes will impact testing and how we will deliver high quality/reliability products in the future. In this talk, I'll give my view on what Testing will be like 8 years from now. Now is the time to start planning for these changes. · Products will be a heterogeneous mix of IC components from multiple foundries - each built using technologies optimized for cost and performance - combined into a final component where this complexity is not apparent in the final application. · Products will adapt themselves to process variation, circuit marginalities, environmental changes and aging - thereby simplifying Testing and achieving superior fault tolerance and power/performance. · Data & Analytics will drive all production processes with particular improvement in exploiting real-time adaptation during the testing & manufacturing process. Testing will be viewed more as a production personalization and data collection process (driving fab/design improvements) - than just sorting pass/failing dies.

A large end-to-end database was created by joining an IC test factory database with a board contract manufacturer (CM) database using the unique electrical identity fused into the IC and read at IC and CM test steps. A new rank correlation method was used to measure statistical dependencies of IC failure rates in the CM factory on failure rates and attributes measured in the IC factory. IC factory dependency, including radial wafer symmetry, was seen in the CM data providing opportunity to improve CM failure rate at the cost of IC yield. A special kind of receiver operating characteristic (ROC) was constructed to quantify the IC factory yield cost of CM failure rate improvements for hypothetical IC factory screens additional to the screens which generated the database. A screen based on RAM fuse repair count was found to be better than one based on blocking of edge dies.

In this paper, we will present two different applications of “test pattern sampling” for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.

A key issue is how advanced technologies are changing the way we do Testing and the Test Industry in general. There are many reports that the failure mechanisms are changing — and therefore Test much change also in response. For example, it has been reported that systematic feature-driven failures are more prevalent than physical spot defectswhich have historically been targeted during Testing. Advanced technologies are expected to drive Testing to fundamental changes in the Test process. For example, Test will assume more responsibility over time in “product personalization” — customizing each chip based on repair/redundant elements, power/performance tuning and new types of fee-dforward data. (e.g., inline test results, optical inspection data) “Adaptive Testing” will enable automated data-driven methods to optimize Quality/Reliability/Yield Loss/Test Time trad-e offs in real-time during production Testing. There are also emerging changes due to the foundry / fables semiconductor model where Testing requirements may be jointly defined among foundries, IP providers, the chip design/integrator and manufacturing test engineerin. g Clearly, there must be more data shared across companies in the End-to-End supply chain … how will this change testing? In this panel, a set of industry experts will describe their experience with advanced technoloyg nodes (32nm/28nm) and how Testing is changing for these nodes. The discussion will range from specific examples of new failures modes … to changes in Test to detect these failure modes … to broader Test process changes. The panel will also address questions like the following: · What are 1–2 examples of new failure mechanisms that you found at 32nm/28nm ? · How did you change testing because of these new defect types/failure mechanisms ? · What new method of “statistical testing” (Adaptive Testing) have you recently started using ? · 3DIC testing — is it really different ? If so, why ? · Product personalization — is this becoming more prevalent ? If so, what are the new drivers & methods ? · Power/performance optimization — is this driving major changes to the Testing process ? If so, what changes ? · Reliability defect screening — are high voltage & high temperature accelerating still effective & required ? · How should the Test industry change to drive improvements to the End-to-End Test process ? · e.g., more rapid, more detailed, real-time cross-company data sharing?

Physically-aware$N$-detect ($PAN$-detect) test improves defect coverage by exploiting defect locality. This paper presents physically-aware test selection (PATS) to efficiently generate$PAN$-detect tests for large industrial designs. Compared to traditional$N$-detect test, the quality resulting from$PAN$-detect is enhanced without any increase in test execution cost. Experiment results from an IBM in-production application-specific integrated circuit demonstrate the effectiveness of PATS in improving defect coverage. Moreover, utilizing novel test-metric evaluation, we compare the effectiveness of traditional$N$-detect and$PAN$-detect, and demonstrate the impact of automatic test pattern generation parameters on the effectiveness of$PAN$-detect.

This paper proposes methods for taking advantage during voltage-based production test of the capability to control well and substrate (body) biases separately from the chip's VDD and GND. Such control is a by-product of a low-power design strategy that allows parts or all of the chip to go into low-power reduced-leakage states. The proposed test methods use body bias manipulation to increase or decrease transistor threshold voltages. Unlike related methods that rely on weakening transistors, the proposed methods are shown to enhance defect detectability by both weakening and strengthening transistors and by exploiting the ability to weaken/strengthen nfets/pfets separately.

Summary Industry test experts will provide their views on how the test is going to change in the next 10 years. Topics will cover the future of Test Equipment, Design-for-Test, EDA software, Foundry Test Support and Test Methods. This panel will describe fundamental changes in the test field and the long-term impacts of these changes. Panelists will also describe how these trends are driving emerging business opportunities. The panelists will make provocative predictions in a way that is never seen in formal papers or presentations.

This paper presents a method using only the rank of the measurements to separate a part's elevated response to parametric tests from its non-elevated response. The effectiveness of the proposed method is verified on the 130nm ASIC. Good die responses are correlated for same parametric tests at different conditions such as temperature, voltage and or other stress. Nonparametric correlation methods are used to calculate the intra-die correlation. When intra-die correlation is found to be low the elevated vectors that lower correlation are extracted and input to IDDQ-based diagnostic tools. Monte-Carlo simulations are described to obtain confidence bounds of the correlation for good die test response.

Physically-aware N-detect attempts to improve the detection characteristics of traditional N-detect by exploiting the localized characteristics of defects. Specifically, in addition to detecting each fault N times, we also require that the physical neighborhood surrounding the target change state as well. In this work, the effectiveness of the physically-aware metric is examined using two approaches. First, tester responses from an in-production IBM chip are analyzed to compare the physically-aware N-detect test with other traditional tests that include stuck-at, IDDQ, logic BIST, and delay tests. Second, diagnostic results from LSI chip failures are utilized to directly compare the traditional and physically-aware N-detect metrics. Results from both experiments demonstrate the effectiveness of physically-aware N-detect test in detecting defects in modern industrial designs.

Studies by previous researchers using production test data reported that not all the production test patterns applied detected defective chips. Researchers found that 70% to 90% of their production test patterns seemed useless because these patterns detected no defective chips and they could therefore be removed without impacting test quality. Previous researchers qualitatively explained this finding by a lack of correlation between test metrics and defect coverage. Notwithstanding the lack of correlation between test metrics and defect coverage, in this paper we develop a simple statistical model that relates the expected number of useless patterns to the production yield, the defect coverage characteristics, and the number of tested chips. This model demonstrates that for practical values of production yield, defect coverage and number of chips tested, a significant fraction of test patterns will be useless. We validated this statistical model by comparing its results with actual production testing data.

Achieving excellent reliability at reasonable cost is a daunting challenge for high-performance processors on advanced technologies. Major issues are lack of high/low voltage margin, huge leakage currents (particularly at burn-in/stress voltages and temperatures) and new failure modes. In this session, we will have three presentations from industry experts who are on the front lines working on these issues.

Business demand for ultra-low defects-permillion (DPM) levels and the emergence of subtle defects that often manifest as functional errors only in the presence of certain specific environmental conditions such as crosstalk, have led to a critical need for intelligent, adaptive, and targeted defectoriented test. The classical model of test, in which integrated circuits (ICs) are subjected to a blanket suite of stuck-fault, transition and Iddq test patterns generated without consideration to layout and chip-to-chip differences are now insufficient to bring DPM levels for cutting-edge ICs down to the requisite 10-100 range demanded by qualityconscious customers.

The methods that are required to meet aggressive DPM objectives are thorough delay tests, very high coverage test patterns, IDDQ test, RAM tests, multiple temperature tests, functional tests, statistical methods, parametric test limits, customer specific tests, DFT. The trade-offs of driving quality levels to <100 DPM include yield loss, schedule impacts, engineering costs.

A top priority for IC producers is achieving high yields - particularly early in the product lifetime. "Yield learning rate" (on real products) is the key differentiator among IC suppliers. Testing must play a larger role in driving yield learning - which change the testing methods, ATE requirements and how the IC business views the value of testing.

This work demonstrates IDDQ signature analysis of random and systematic defects, including yield detractors and reliability defects. Application is demonstrated for both understanding failure root cause and guiding test decisions. IDDQ signatures contain rich information about the circuit, defect behavior and processing conditions. This paper describes capturing that information by classifying signatures into different categories and using the classifications to learn about the nature of the defects occuring on a variety of ASIC chips.

Over the last 2-3 years, there has been a major change in the IC industry from being predominantly "functional-based testing" to being predominantly "scan-based testing" (for new design starts). The question has now changed to: "can we completely avoid functional testing?" The same trends that are driving companies toward scan-based testing will also drive them to completely avoid functional-based testing. The advantages of structural testing cannot be fully exploited unless at-speed functional testing is avoided. The move away from functional testing will happen in stages. Some companies are already avoiding functional test for some test insertions - but not all. For example, some products are currently tested with scan-based, reduced pincount testing at wafer level - but still require full pincount, scan+functional testing at package test.

A weak chip is one that contains flaws-defects that do not interfere with correct circuit operation at normal conditions but may cause intermittent or early-life failures. MINVDD testing can detect weak CMOS chips. The minvdd of a chip is the minimum supply voltage value at which a chip can function correctly. It can be used to differentiate between good chips and weak chips. In the first part of this paper, we will study several types of flaws to demonstrate the effectiveness of MINVDD testing. Experimental results show that MINVDD testing is as effective as VLV testing for screening out burn-in rejects. In the second part of this paper, we propose test conditions for low voltage testing, including test voltage, test timing and test sets. Experimental results are presented to validate our proposal.

Understanding the effectiveness of their production tests is a critical task for IC suppliers. Numerous trends suggesting that conventionally applied test methods must change to meet future needs will make the task even more critical-and difficult-in the future. This paper presents characterization and diagnostic data and ideas aimed at helping IC suppliers understand test effectiveness.

SEMATECH has sponsored a "Test Method Evaluation" study to understand the trade-offs among the most common test methodologies used in the industry. This paper presents the results of the failure analysis portion of that project. The testing, reliability stressing, characterization, fault diagnosis and physical analysis results are presented for 25 devices including "IDDq-only" failures and "delay test-only" failures.

Technological advances such as flip-chip packaging, multiple hierarchical wiring planes, and ultra-high frequencies reduce the effectiveness of conventional diagnostic techniques. It has recently been demonstrated that light pulses emitted during circuit switching can be used to characterize the behaviour of integrated circuits. In this paper, a new method of circuit characterization using this technique is described. An example of the diagnosis of a timing failure caused by a resistive path to a single transistor is described.

There will inevitably be much debate about the accuracy of the 1997 SIA Roadmap. Will we be building devices of 100M transistors that go at frequencies of a GHz by the year 2002-or will it happen later? Although many of the actual numbers and dates will be different than predicted in the SIA Roadmap, some key trends are obvious and will inevitably impact testing methods. These key trends include: increased design speeds, increased circuit densities, reduced time-to-market, increased integration of functional macros (systems-on-a-chip), and increased leakage currents. The SIA Roadmap trends suggest that functional testing will hit a number of barriers.

SEMATECH has sponsored a "test method evaluation" study to understand the trade-offs among the most common test methodologies used in the industry. This paper presents the results of the failure analysis portion of that project. The testing, reliability stressing, characterization, fault diagnosis and physical analysis results are presented for 25 devices including "IDDq-only" failures and "delay test-only" failures.

A current disadvantage of IDDq testing is lack of software-based diagnostic tools that enable IC vendors to create a large database of defects uniquely detected with this test method. We present a methodology for performing defect localization based upon IDDq test information (only). Using this technique, fault localization can be completed within minutes (e.g. <5 minutes) after IC testing is complete. This technique supports multiple fault models and has been successfully applied to a large number of samples-including ones that have been verified through failure analysis. Data is presented related to key issues such as diagnostic resolution, hardware-to-fault model correlation, diagnostic current thresholds, and the diagnosability of various defect types.

The SEMATECH "Test Methods Evaluation" study, Project Number S-121, is an experiment to determine the relative merits of several test methodologies often used by SEMATECH member companies and other IC manufacturers. Conclusions drawn from the experiment thus far have indicated that each test methodology uniquely detects defects. This experimentation and analysis would not have been possible outside a consortium setting such as SEMATECH. Its conclusions may affect other major segments of the industry, including ATE manufacturers, CAD vendors, and academia. This paper gives a brief overview of the experiment and summarizes its findings.

Die screening based on the locality of defects has long been informally practised in the industry whereby dice from wafers, or parts of the wafer, that display high defect levels are discarded. More recently this approach has been refined such that test results for neighbouring dice on the wafer are also considered in evaluating test results for a particular die. It has been shown in principle, using negative binomial statistics for defect distributions on wafers, that such an approach can much better optimize test costs and screen for low defect levels in bare dice and packaged chips. In this paper we present, for the first time, experimental test data to demonstrate the effectiveness of this new approach. Our results are based on extensive testing of 4784 dice on 23 wafers from an IBM process. We show that bare die screening based on defect clustering considerations can significantly reduce defect levels in dice that pass wafer probe tests. This approach also has the potential to screen out burn-in failures. Thus it offers new low cost strategies for delivering high quality "known- good" die (KGD) for MCM applications.

This paper describes an experiment in which various semiconductor test methodologies (stuck-fault, functional, delay and IDDq) are applied to an ASIC device. The goal of this project is to provide the data that will enable manufacturers to optimize their application of the various tests. This project was supported through SEMATECH (Project S-121, "Semiconductor Test Method Evaluation ").

Supplying cost effective testing for large application specific integrated circuits (ASICs) is one of the key challenges facing the semiconductor industry. Projections suggest that it will not be cost effective to continue in the current test direction. ASIC suppliers must be able to offer a flexible, cost-effective set of test solutions that will meet a variety of customer requirements. This paper presents some of the trade-offs used in developing optimal test strategies.

Conventionally, test vectors are generated using gate-level models to represent the circuit design and abstract fault models (e.g. the stuck-fault model) to describe all of the processing defects causing circuit failure. The authors demonstrate that test vectors can be generated using realistic defect models and actual IC layouts, which should lead to test vectors with a higher defect detectability. The layout-driven generation of the faults has a computational complexity which is similar to that of design-rule checking, i.e. O(n log n).>

A testing methodology which applies built-in current sensors to detect abnormal currents in the power buses of functional blocks of CMOS ICs is proposed, that significantly improves the quality of VLSI circuit testing. A summary of simulation results and design experiments is presented to demonstrate the feasibility and to illustrate the applicability of the approach. The results suggest that built-in current testing could be a very powerful tool for overcoming basic bottlenecks in VLSI testing, providing very inexpensive testing, high-quality built-in testing, or on-chip concurrent reliability testing for high-quality fault-tolerant systems.>

In a typical approach to VLSI testing, open faults are modeled by the transistor-stuck-open fault model or are not explicitly covered at all. It is shown that functional faults caused by opens, i.e. by regions with missing material, cannot be modeled well by a transistor stuck-open. It is also shown that the majority of opens which occur in CMOS static circuits manifest themselves as timing faults. The analysis of the behavior of a CMOS transistor with a floating gate indicates it acts as a weakly 'on' active load, and therefore an open gate cannot be detected by stuck-fault testing but could be detected by monitoring the static current through the power buses.>

Built-in current (BIC) testing involves the monitoring of power bus currents in a VLSI circuit, as a means of detecting processing defects in the circuit. The design and performance of a prototype BIC sensor for static CMOS are discussed. It has been demonstrated that a fully-operational BIC sensor can be designed using a standard CMOS process. The presented design met all basic requirements: it was small, it caused only a small degradation of the performance of the monitored module, and it provided sufficient current resolution. The main disadvantage of the described design, however, was a substrate current caused by the structure of the bipolar transistor.>