In high-performance chip design, the problem of net matching is often critical for achieving correct circuit performance. We adopt a conservative design, to route all matched nets with identical topologies and equal wire lengths to achieve zero skew. The problem is formulated as a variant of the D-dimensional Steiner tree problem. We propose a two-stage solution. The first stage uses an iterative improvement strategy to generate the Steiner tree topology for all the nets. The second stage places the nodes using one of two methods. The first approach expresses the optimal Steiner node positions as a linear programming solution, with average computational complexity O(n/sup 2/m/sup 2/), where n is the number of nets and m is the number of pins. Improved efficiency is achieved under the other approach by transforming the Manhattan metric to an l/sub /spl infin// norm using a 45/spl deg/ rotation of the solution space. The norm is then approximated by either an l/sub /spl lambda// norm, for suitably large values of /spl lambda/, or an exponential "penalty" function. The solution space in both approaches becomes strictly convex, allowing us to apply a greedy approach which converges to an optimal solution with great efficiency, leading to a dramatic speed-up versus the linear programming approach.

A two-dimensional compaction algorithm is presented which is developed primarily for placement refinement of a building-block layout. For a given placement, a mixed-adjacency graph is derived and then a set of graph operations are applied to the graph to accomplish two-dimensional compaction. The placement can be updated efficiently in the geometric domain because of the one-to-one correspondence between the mixed-adjacency graph and the title representation of the placement. Some pertinent properties of the mixed-adjacency graph and one-dimensional compaction using the graph model are also explored.>

In high-speed VLSI design, the matching of signal net lengths is often critical to the proper performance of a circuit. Given a design which specifies groups of signal nets to be matched, a physical layout must be generated which conforms to these constraints. Different aspects of the problem in VLSI design layout are investigated, and the approaches used to automate the process are presented.>

A topological method for two-layer routing of printed circuit boards and VLSI chips is presented. The primary criterion is via minimization. Multiterminal nets and multiple wires are allowing to intersect at any via. After topological routing, the via minimization problem is then formulated as a (0, 1) linear programming problem and solved. The time and space complexities of the algorithm are O(n/sup 2/) and O(n+k), respectively, where n is the number of terminals in the routing region and k is the total number of cross points and via candidates.>

A new algorithm for channel spacing is discussed in this paper. In contrast to existing compaction algorithms, we rely on the geometric method and bypass the constraint graph during the whole spacing process.