Demo Data from EDBT 2026 / reviewers in the wild / expert
Francisco J. O. Dias
dblp:35/6425
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1976
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 89% Hardware reliability and fault tolerance · 11% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
fault detection |
0.0 | 2 | 1976 | Truth-Table Verification of an Iterative Logic Array · IEEE Trans. Computers 1976 Fault Masking in Combinational Logic Circuits · IEEE Trans. Computers 1975 |
Electronic design automation
hardware verification and test |
0.0 | 2 | 1976 | Truth-Table Verification of an Iterative Logic Array · IEEE Trans. Computers 1976 Fault Masking in Combinational Logic Circuits · IEEE Trans. Computers 1975 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 2 | 1976 | Truth-Table Verification of an Iterative Logic Array · IEEE Trans. Computers 1976 Fault Masking in Combinational Logic Circuits · IEEE Trans. Computers 1975 |
Electronic design automation › hardware verification and test › combinational circuit testing
iterative logic array testing |
0.0 | 1 | 1976 | Truth-Table Verification of an Iterative Logic Array · IEEE Trans. Computers 1976 |
Hardware reliability and fault tolerance
fault masking |
0.0 | 1 | 1975 | Fault Masking in Combinational Logic Circuits · IEEE Trans. Computers 1975 |
Electronic design automation › hardware verification and test › fault detection
multiple fault detection |
0.0 | 1 | 1975 | Fault Masking in Combinational Logic Circuits · IEEE Trans. Computers 1975 |
Methods — techniques the papers use, named apart from their topics
fault analysis model · 0.0algebraic procedure · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1976 | Truth-Table Verification of an Iterative Logic ArrayabstractThis paper studies the problem of fault detection in iterative logic arrays (ILA's) made up of combinational cells arranged in a one-dimensional configuration with only one direction for signal propagation. It is assumed that a fault can change the behavior of the basic cell of the array in an arbitrary way, as long as the cell remains a combinational circuit. It is further assumed that any number of cells can be faulty at any time. In this way, testing an array is equivalent to verifying the correctness of its truth table. That could be done exhaustively through the application of a set of tests whose size is exponential in N, the number of cells in the array. The procedure presented in this paper generates a test set whose size is constant (i.e., independent of the number N of cells in the array). Conditions (on the structure of the basic cell) for the application of this procedure are presented. A practical example illustrating the application of this procedure is presented. Bounds for the size of the derived test set are presented and it is shown how to modify the basic cell of an arbitrary array in order to test it with a constant number of tests. Francisco J. O. Dias |
IEEE Trans. Computers | 1 |
| 1975 | Fault Masking in Combinational Logic CircuitsabstractAn important problem in fault detection is to verify whether a single-fault test set is able to detect all multiple-faults. This paper provides a solution to the above problem. It is known that a test set derived for the detection of some fault may fail this purpose in the presence of an additional fault. This phenomenon is called masking among faults, and is of great importance in the derivation of a test set which detects all multiple-faults. This paper investigates the masking relations among faults in a combinational logic circuit. For this purpose a transform for the circuit is defined and a model for fault analysis is constructed. This transform and model reduce the number of faults which have to be considered in order to achieve the detection of all multiple-faults. An algebraic procedure yields the derivation of the masking relations. A problem which arises, namely the existence of a set of faults forming a loop of masking relations is considered. An application is presented: starting with a test set derived under the single-fault assumption it is shown how to extend this test set so that it detects all multiple-faults. All of the results in this paper are valid for general multiple-output circuits. For simplicity in the exposition, the single-output case is examined. Francisco J. O. Dias |
IEEE Trans. Computers | 1 |