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Mehmet A. Cirit

dblp:35/6624 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 62% Integrated circuit design · 38%

Topics — the 11 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits		 0.011989
The Meyer model revisited: why is charge not conserved? [MOS transistor] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Integrated circuit design
charge conservation		 0.011989
The Meyer model revisited: why is charge not conserved? [MOS transistor] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation
circuit simulation		 0.011989
The Meyer model revisited: why is charge not conserved? [MOS transistor] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Integrated circuit design › analog and mixed-signal circuits › device modeling
MOSFET modeling		 0.011989
The Meyer model revisited: why is charge not conserved? [MOS transistor] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation › circuit simulation › analog circuit simulation
SPICE simulation		 0.011989
The Meyer model revisited: why is charge not conserved? [MOS transistor] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation
hardware verification and test		 0.011988
Switch Level Random Pattern Testability Analysis · DAC 1988
Electronic design automation › hardware verification and test
random testing		 0.011988
Switch Level Random Pattern Testability Analysis · DAC 1988
Electronic design automation › hardware verification and test
testability analysis		 0.011988
Switch Level Random Pattern Testability Analysis · DAC 1988
Integrated circuit design
digital circuit design		 0.011987
Transistor Sizing in CMOS Circuits · DAC 1987
Electronic design automation
physical design		 0.011987
Transistor Sizing in CMOS Circuits · DAC 1987
Electronic design automation › circuit sizing
transistor sizing		 0.011987
Transistor Sizing in CMOS Circuits · DAC 1987

Methods — techniques the papers use, named apart from their topics

nodal analysis · 0.0meyer capacitance model · 0.0optimization algorithm · 0.0RC-tree approximation · 0.0
YearPublicationVenuePosition
1989 The Meyer model revisited: why is charge not conserved? [MOS transistor]
abstract
A new approach to computer simulation of capacitance effects in MOS transistors is presented. It is shown that charge nonconservation is the result of faulty mathematical modeling of the capacitive nonlinearities in the SPICE circuit simulator and is not intrinsic to any specific charge or capacitance model. The correct mathematical model is described. The results of computer simulations using the Meyer capacitance model, which conserves charge, are given for some test circuits.>
Mehmet A. Cirit
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1988 Switch Level Random Pattern Testability Analysis
Mehmet A. Cirit
 DAC1
1987 Transistor Sizing in CMOS Circuits
abstract
The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.
Mehmet A. Cirit
 DAC1