A low power passive equalizer using RL terminator is proposed and optimized in this work. The equalizer includes an inductor in series with the resistive terminator, which boosts high frequency components and therefore improves the interconnect bandwidth with little overhead on power consumption. An analytic estimation method for eye-opening and jitter based on tritonic step response is also introduced in this work, which enables the optimization procedure. Our experimental results show that our estimation method is accurate and a board level transmission line of 50cm wire length can achieve 15Gb/s data rate. With 15GHz frequency input, the power consumption of the equalizer is less than 2.5mW, and the total power is 5mW.

This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for EMC and signal integrity simulations. A practical modeling process is proposed and applied to some example devices. The modeling process is simple and efficient, and it yields models performing at a very high accuracy level.

The design rule formulation for the switching noise containment in a high-performance machine is presented in this paper. This design rule is expressed as an algebraic inequality and condenses the information on the generation and propagation of the switching noise in a multichip carrier to a form that is directly usable for the logic design of a computing machine. The statistics associated with the two quantities essential for the rule derivation, namely, noise generation and noise tolerance, are explained. The methodology necessary for the development of this rule is also described. The experimental procedure used for the verification of this methodology is highlighted.