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Sreekrishna Madhwapathy

dblp:35/6842 · DBLP profile ↗
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6ranked-venue papers
2as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%
Theoretical computer science
1 paper
Algorithms and data structures · 50% Graph algorithms and graph theory · 50%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › routing › channel routing
over-the-cell routing
0.021996
Optimal algorithms for planar over-the-cell routing problems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
A Unified Approach to Multilayer Over-the-Cell Routing · DAC 1994
Electronic design automation
physical design
0.021996
Optimal algorithms for planar over-the-cell routing problems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
A Unified Approach to Multilayer Over-the-Cell Routing · DAC 1994
Algorithms and data structures
dynamic programming
0.011996
Optimal algorithms for planar over-the-cell routing problems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Graph algorithms and graph theory › planar graphs
maximum planar subset
0.011996
Optimal algorithms for planar over-the-cell routing problems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Electronic design automation › physical design › routing
multilayer routing
0.011994
A Unified Approach to Multilayer Over-the-Cell Routing · DAC 1994
Electronic design automation › physical design
routing
0.011994
A Unified Approach to Multilayer Over-the-Cell Routing · DAC 1994

Methods — techniques the papers use, named apart from their topics

parallel algorithm · 0.0dynamic programming · 0.0approximation algorithm · 0.0unified routing approach · 0.0
YearPublicationVenuePosition
1996 Optimal algorithms for planar over-the-cell routing problems
abstract
In this paper, we consider the two row maximum planar subset (TRMPS) problem in over-the-cell routing. The TRMPS problem requires selection of the maximum planar subset of nets, which can be routed between two rows of terminals in a cell row. This problem was first encountered by Gong, Liu, and Preas (1990). They stated the complexity of this problem to be unknown, and presented a min {1,k/d(S)} approximation algorithm, where k is the number of tracks available over the cell area and d(S) is the density of a solution S. We show that TRMPS problem can be solved optimally in polynomial time. We present a O(kn/sup 2/) dynamic programming algorithm for the TRMPS problem, where n is the number of nets. We also present a parallel version of our algorithm, which has a complexity of O(kn). Our algorithm can also be extended to solve the TRMPS problem, in the presence of prerouted nets, a chosen subset of nets, as well as for planar channel routing. We also apply our technique to obtain a 0.5 approximation, for over the cell routing in middle terminal model, thus improving the best known existing algorithm. The weighted version of the TRMPS problem, as well as, all the extensions can also be solved in O(kn/sup 2/) time.
Srinivasa R. Danda, Sreekrishna Madhwapathy, Anand Panyam, Naveed A. Sherwani, Ioannis G. Tollis
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
1995 OPRON: a new approach to planar OTC routing
abstract
In this paper we solve the planar over-the-cell routing problem, in which nets must have at least one terminal on the boundary. Such nets allow for nontraditional cell designs, where all terminals must be placed on the boundaries giving a degree of freedom to the cell designer. We present a dynamic programming algorithm that optimally solves this problem, in O(K/sup 2/n/sup 4/) time, where K is the number of tracks available over the cell for a given cell row region, and n is the number of nets to be routed.
Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani, Aman Sureka
Great Lakes Symposium on VLSI2
1994 A Unified Approach to Multilayer Over-the-Cell Routing
abstract
Several Ov er-the-Cell (OTC) routing algorithms have been proposed for two and three layer processes.All the existing OTC routers can be used only on the cell models for whic h they were developed for.In this paper, we develop a uni ed approach t o m ulti-layer routing, motiv ated by o v er-the-cell routing, which can be used for full-custom la youts.Our approac h can also be directly applied to standard cell layouts, irrespective of the cell model used in the design.Our router has been implemen ted in C and tested on industrial benchmarks, suc h as PRIMARY I and PRIMARY I I , for which it obtained channel-less layouts.
Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam
DAC1
1994 An optimal algorithm for maximum two planar subset problem [VLSI layout]
abstract
The Two Row Maximum Planar Subset (TRMPS) problem asks for finding the maximum planar subset of nets, that can be routed between two rows of terminals an a cell row. This problem was first encountered by Gong, Liu, and Preas (1990). They declared it open, and presented an approximation algorithm for this problem. In this paper we show that TRMPS problem can be solved optimally in polynomial time, and we present an O(kn/sup 2/) algorithm to solve this problem. Our algorithm can also be extended to solve the TRMPS problem, in the presence of pre-routed nets, a chosen subset of nets, as well as for planar channel routing. We also apply our technique to obtain an improved approximation algorithm, for over the cell routing in middle terminal model standard cell layouts.>
Anand Panyam, Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani
Great Lakes Symposium on VLSI3
1994 A Hierarchical Approach to Clock Routing in High Performance Systems
abstract
In this paper, we present an hierarchical clock routing scheme, which minimizes the longest source to sink path, and obtains a path balanced clock tree with minimal total wirelength. Our scheme takes into consideration, the hierarchical design of a circuit. Our approach is applicable to large VLSI circuits and MCM's. The algorithm has been implemented and experimental results are encouraging.>
Sreekrishna Madhwapathy, Naveed A. Sherwani
ISCAS2
1994 An Efficient Four Layer Over-the-Cell Router
abstract
Several Over-the-Cell (OTC) routing algorithms have been proposed for two and three layer processes. All the existing OTC routers assume that the terminals are laid out in a specific predetermined fashion. These restrictions on the terminals complicate the task of cell design and increase the width of the cells. In this paper, we develop a four layer OTC router which allows arbitrary terminal locations. Freed from fixed terminal placement restrictions, cell designers can aim to design with minimum width. Our router has been implemented and tested on several circuits. For most of the circuits, it obtained channel-less layouts.>
Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam
ISCAS1