Demo Data from EDBT 2026 / reviewers in the wild / expert
Jaeyong Park
dblp:35/7218
· DBLP profile ↗
6ranked-venue papers
3as first author
4since 2021 · last 2025
0009-0001-4373-3963ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 3 · 1 first-author · 2 since 2021Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 40% Hardware accelerators and domain-specific architectures · 40% Energy-efficient computing · 20% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › machine learning accelerator
DNN training accelerator |
0.9 | 1 | 2025 | TM-Training: An Energy-Efficient Tiered Memory System for Deep Learning Training in NPUs · ACM Trans. Storage 2025 |
Energy-efficient computing
memory energy efficiency |
0.9 | 1 | 2025 | TM-Training: An Energy-Efficient Tiered Memory System for Deep Learning Training in NPUs · ACM Trans. Storage 2025 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
neural processing unit |
0.9 | 1 | 2025 | TM-Training: An Energy-Efficient Tiered Memory System for Deep Learning Training in NPUs · ACM Trans. Storage 2025 |
Memory systems
tiered memory |
0.9 | 1 | 2025 | TM-Training: An Energy-Efficient Tiered Memory System for Deep Learning Training in NPUs · ACM Trans. Storage 2025 |
Memory systems › tiered memory
tiered memory management |
0.9 | 1 | 2025 | TM-Training: An Energy-Efficient Tiered Memory System for Deep Learning Training in NPUs · ACM Trans. Storage 2025 |
Methods — techniques the papers use, named apart from their topics
static data placement · 0.9data splitting · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | TM-Training: An Energy-Efficient Tiered Memory System for Deep Learning Training in NPUsabstractDRAM accounts for a large fraction of the total cost of ownership of memory systems in deep learning acceleration systems. To achieve sustainable scalability, tiered memory systems with denser technologies become critical. Prior work has proposed various tiered memory systems, but no matter how a system is designed, data movements between tiers consume substantial energy. In particular, as model sizes and memory capacity demands grow, the data movements between memory tiers become more frequent, posing a challenge that tiered memory systems may reduce deployment costs but suffer from low energy efficiency. If a memory system proactively places data into a tier and timely fetches it from the tier, then the excessive data movement between tiers can be mitigated. We find that a system can statically anticipate such behaviors for all pages and localities. With this insight, we propose a new DNN acceleration system called TM-Training using flash memory. TM-Training capitalizes on the repetitive nature of the same computational patterns during execution, enabling the static establishment of optimal data placement for subsequent operations. Moreover, TM-Training employs a new data-splitting scheme to enable precise memory management. Our evaluation demonstrates that TM-Training reduces inter-tier data traffic by 64% and achieves a 55% higher throughput per watt in training than prior work. Jaeyong Park, Sangun Choi, Gunjae Koo, Myung Kuk Yoon, Yunho Oh |
ACM Trans. Storage | 1 |
| 2024 | VitBit: Enhancing Embedded GPU Performance for AI Workloads through Register Operand PackingabstractThe rapid advancement of Artificial Intelligence (AI) necessitates significant enhancements in the energy efficiency of Graphics Processing Units (GPUs) for Deep Neural Network (DNN) workloads. Such a challenge is particularly critical for embedded GPUs, which operate within stringent power constraints. Traditional GPU architectures, designed to support a limited set of numeric formats, face challenges in meeting the diverse requirements of modern AI applications. These applications demand support for various numeric formats to optimize computational speed and efficiency. This paper proposes VitBit, a novel software technique designed to overcome these limitations by enabling efficient processing of arbitrary integer format values, especially those 8 bits or fewer, which are increasingly prevalent in AI workloads. VitBit introduces two key innovations: the packing of arbitrary integer formats for parallel computation and the simultaneous execution of Tensor cores, INT and FP (Integer and Floating-Point) CUDA cores. This approach leverages the architectural features of modern GPUs, such as those based on NVIDIA Ampere architecture, which allows concurrent operation of FP32 and INT32 cores at full throughput. Our evaluation of VitBit on NVIDIA Jetson AGX Orin demonstrates substantial improvements in arithmetic density and peak throughput, achieving up to a 22% reduction in execution time for benchmark AI workloads without compromising inference accuracy. VitBit effectively bridges the gap between current hardware capabilities and the computational demands of AI, offering a scalable and cost-effective method for enhancing GPU performance in AI applications. Jaebeom Jeon, Minseong Gil, Junsu Kim 0005, Jaeyong Park, Gunjae Koo, Myung Kuk Yoon, Yunho Oh |
ICPP | 4 |
| 2022 | Hybrid Beamforming for Intelligent Reflecting Surface Aided Millimeter Wave MIMO SystemsabstractAs communication systems that employ millimeter wave (mmWave) frequency bands must use large antenna arrays to overcome the severe propagation loss of mmWave signals, hybrid beamforming has been considered as an integral component of mmWave communications. Recently, intelligent reflecting surface (IRS) has been proposed as an innovative technology that can significantly improve the performance of mmWave communication systems through the use of low-cost passive reflecting elements. In this paper, we study IRS-aided mmWave multiple-input multiple-output (MIMO) systems with hybrid beamforming architectures. We first exploit the sparse-scattering structure and large dimension of mmWave channels to develop the joint design of IRS reflection matrix and hybrid beamformer for narrowband MIMO systems. Then, we generalize the proposed joint design to broadband MIMO systems with orthogonal frequency division multiplexing (OFDM) modulation by leveraging the angular sparsity of frequency-selective mmWave channels. Simulation results demonstrate that the proposed joint designs can significantly enhance the spectral efficiency of the systems of interest and achieve superior performance over the existing designs. Sung Hyuck Hong, Jaeyong Park, Junil Choi |
IEEE Trans. Wirel. Commun. | 2 |
| 2022 | Practical Channel Estimation and Phase Shift Design for Intelligent Reflecting Surface Empowered MIMO SystemsabstractIn this paper, channel estimation techniques and phase shift design for intelligent reflecting surface (IRS)-empowered single-user multiple-input multiple-output (SU-MIMO) systems are proposed. The two novel channel estimation techniques proposed in the paper, single-path approximated channel (SPAC) and selective emphasis on rank-one matrices (SEROM), have low training overhead to enable practical IRS-empowered SU-MIMO systems. SPAC is mainly based on parameter estimation by approximating IRS-related channels as dominant single-path channels. SEROM exploits IRS phase shifts as well as training signals for channel estimation and easily adjusts its training overhead. A closed-form solution for IRS phase shift design is also developed to maximize spectral efficiency where the solution only requires basic linear operations. Numerical results show that SPAC and SEROM combined with the proposed IRS phase shift design achieve high spectral efficiency even with low training overhead compared to existing methods. Sucheol Kim, Hyeongtaek Lee, Jihoon Cha, Jaeyong Park, Junil Choi |
IEEE Trans. Wirel. Commun. | 5 |
| 2013 | UML design pattern metamodel-level constraints for the maintenance of software evolutionabstractSUMMARY Software maintenance including design is difficult because it is usually performed on someone else's work over a period of time. Maintaining a pattern‐based design is especially much more difficult when the information on specific patterns that have been used are not available in the corresponding design documents. Also, finding a maintainer who has a similar level of knowledge on specific patterns that the initial designer had is not easy. Pattern‐based design, the use of design patterns during the software design process, has become widely used in the object‐oriented community because of its many benefits such as its reuse. However, the defects in pattern‐based design can be introduced during the design maintenance phase when the changes are made to the requirements and the initial design, but the conformance to the original patterns is neglected. This conformance process is laborious and time consuming; no systematic process exists to guide the defects discovery and maintenance. Also, deep and correct knowledge of design patterns and their characteristics are required because this process is conducted by human experts. Failure to follow this conformance process and to maintain correct designs during software design evolution may cause serious problems in later software development and maintenance stages by not providing the benefits of pattern‐based design that would have been possible if followed correctly. There is a strong need of a systematic design and maintenance method for preventing defects in design patterns introduced during the evolution of pattern‐based software design and its maintenance. Because conventional UML design methods do not provide such systematic ways of assessing pattern‐based design conformance to the evolutionary changes, we have developed the pattern instance changes with UML profiles (PICUP) design method, which is an improved design method for perfective and corrective UML pattern‐based design maintenance and assessment. Design pattern in UML profiles (DPUP) is developed for the use of instantiation, maintenance, and assessment of UML pattern‐based designs to support the formal specification of a design pattern. DPUPs, as the main part of the PICUP design method, provide metamodel‐level UML design constraints using UML stereotype notations and metamodel‐level Object Constraint Language design constraints. Assessment of pattern‐based designs in UML class diagram with the corresponding DPUPs enforces maintainers to make necessary and correct changes to keep the principles of the original designs. Pattern‐related information is annotated using stereotype notations to help assess pattern‐based designs when changes are made. Furthermore, the structural conformance checking of a given UML pattern‐based design can be automated by using the assessment tool. The major contributions of this paper are: (i) specifying design patterns using extended UML profile; (ii) providing a means of how to instantiate pattern‐based designs from DPUPs with naming conventions; and (iii) providing design constraints for maintaining pattern‐based design to guide correct changes of a given design in PICUP method. Explanatory type case studies were performed to better understand and evaluate the effectiveness of the PICUP design method with DPUPs. Answers to the case study questionnaires and the pattern defects discovered from the case studies support the hypothesis that the PICUP method is an improved design method that ensures structural conformance of UML pattern‐based designs to the corresponding design patterns during perfective and corrective design maintenance for software systems. Copyright © 2011 John Wiley & Sons, Ltd. Jaeyong Park, Seok Won Lee, David C. Rine |
Softw. Pract. Exp. | 1 |
| 2011 | Construction of phase tracking codebooks based on the Lloyd-Max vector quantizationabstractIn this paper, we propose a codebook construction method for multiple-input multiple-output (MIMO) beamforming systems operating under the per-antenna power constraint (PAPC). Under the PAPC which limits the individual power of each transmit antenna, it is known that only phase steering information is required to form the optimal beamforming vector at the transmitter. For systems with non-reciprocal uplink and downlink channels, the optimal phase steering information should be chosen at the receiver based on the estimated channel state information, and fed back to the transmitter through rate-limited feedback links. To efficiently encode the phase steering information in the feedback messages, phase steering codebooks have been previously proposed in the literature. In order to exploit the temporal correlation property of the wireless fading channels, we propose to use the phase tracking information between adjacent feedback slots as feedback messages, and provide the construction algorithm for the phase tracking codebook. The objective function for the phase steering codebook is reformulated as a new objective function for the phase tracking codebook to apply the generalized Lloyd-Max vector quantization (VQ) algorithm. The performance of the two codebooks is evaluated and the effectiveness of the proposed codebook is demonstrated by Monte-Carlo simulations. Jaeyong Park, Hyung-gil Yoo, Wonjin Sung |
WCNC | 1 |