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Devada Varma

dblp:35/7863 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Embedded and real-time systems · 77% Reconfigurable computing and FPGAs · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Embedded and real-time systems
signal processing systems		 0.112010
Programming high performance signal processing systems in high level languages · FPGA 2010
Reconfigurable computing and FPGAs
FPGA-based signal processing		 0.012010
Programming high performance signal processing systems in high level languages · FPGA 2010

Methods — techniques the papers use, named apart from their topics

high-level language programming · 0.1
YearPublicationVenuePosition
2010 Programming high performance signal processing systems in high level languages
abstract
No abstract available.
Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro
 FPGA2