Logic Locking aims to hide the original functionality of the design using a secret key. It protects hardware intellectual properties (IPs) against IP piracy or IC overproduction. However, an attacker analyzes the structural traces and/or uses Boolean satisfiability based technique called SAT attack to break such logic locking schemes. This motivates us to find a logic locking technique that can work against both SAT and structural analysis attacks. Therefore, this paper introduces a novel multiplier-based logic locking scheme. Leveraging the inherent complexity of multiplier circuits, the proposed scheme exponentially increases the time required for each iteration of a SAT attack. Moreover, a heuristic is also proposed to identify appropriate locations for inserting multiplier instances to increase the number of iterations. The multiplier-based logic locking scheme is further combined with the Anti-SAT scheme to create a robust and effective defense mechanism against SAT attacks and the various other attacks exploiting structural traces. The proposed technique is resilient to the state-of-the-art attack dedicated to the existing compound logic locking schemes. Moreover, the proposed compound logic locking scheme, requires half the number of key inputs than the state-of-the-art logic locking scheme while providing the similar level of security.

Approximate circuits are widely gaining popularity in various fields where error tolerance is applicable. However, striking the right balance between error tolerance and the output quality is a challenging step in the overall design of approximate systems. We propose a systematic approach utilizing Look-Up Table (LUT)-based netlist transformations to achieve approximation while targeting specific error guarantees. Specifically, we employ a SAT-based property checking technique to accommodate worst-case error constraints acting as error guarantees. The proposed methodology involves the formulation of templates to enable the reusability of the technique for different design choices. The analysis comprises of fitness function evaluation based on layout area or the considered error guarantees. We analyze the impact of different parameters on the quality of the output of the resulting approximation and the time taken to obtain them.

Scan design-for-test (DfT) feature can be exploited as a side channel to break a cryptographic chip. The stringent test and diagnosis requirements of present-day complex system-on-chip (SoC) make use of the scan DfT feature unavoidable. However, being a threat to cryptographic chips, it needs to be secured against the scan-based side-channel attacks. In this paper, we propose a simple yet effective technique to prevent scan attack on Advanced Encryption Standard (AES) cryptographic chip. The proposed technique restricts the user from applying any random inputs at the plain-text inputs. To use the scan feature the plain-text inputs must be forced to a constant all-0 or all-1 value throughout the test session. Because of this feature, there is no possibility of mounting any differential scan attack. The proposed technique is simple to implement and does not have any impact on test coverage.

Scan-based side-channel attacks have been gaining a prominence among the malicious attackers. The unprotected scan chains are extremely vulnerable and could be exploited to extract the secret information from a security chip such as an Advanced Encryption Standard (AES) cryptochip. To protect the secret information from being hacked it is utmost necessary to redesign the scan chain with security features. In this paper, we propose a secure scan architecture aiming at the protection of AES cryptochips against scan-based attacks. The proposed idea is based on the principle of test pattern encryption. The major contribution of our architecture is area efficiency and its security features without hampering test, diagnose, and debug capability of the original scan chain. The experimental results and security analysis shows the efficacy of proposed design.

Test and diagnosis requirements has made the use of scan design unavoidable for present day highly complex circuits. However, scan design can be exploited to retrieve the secret information stored on a crypto chip by mounting scan based side channel attack. The scan design poses a threat to the security of crypto chips as it gives the user the capability to control/observe the circuit state. In this paper, we propose a technique to secure the scan design that can effectively defend the crypto chips against scan based side-channel attacks. To use the scan architecture the user first needs to supply the test authorization key. Once the user is authorized, the conventional test sequence can be started. Furthermore, the proposed technique allows using the original test set without any test time and test data overhead. In addition to that, the proposed technique leaves the debug capability intact and has a marginal area overhead.

Due to tremendous growth in complexity of modern designs, bugs inevitably escape the pre-silicon verification stage. This has led to considerable increase in the time and effort dedicated to post-silicon validation. Debugging designs at postsilicon stage faces a severe bottleneck of limited observability of the internal states. This paper presents a methodology for post-silicon debug utilizing the special features of progressive random access scan (PRAS). The PRAS offers a read-out of nondestructive scan values which is the bottleneck in the process of debugging. The proposed methodology avoids the large overhead of additional resources for debugging as the DfT architecture is reused. PRAS provides a simultaneous solution to the problems of power, data volume and application time during testing at the cost of routing overhead. The PRAS based proposed architecture offers visibility of internal states in fewer clock cycles than traditional serial scan chain based debug methods. The proposed debug scheme offers reconfigurability which enables selective visibility of internal states of a certain portion of the design. Experimental results indicate the better performance of the proposed methodology as compared to the state restoration based observability enhancement techniques.

Over the years, serial scan design has became the defacto Design for Testability (DFT) technique. The ease of testing and high test coverage has made it to gain wide spread industrial acceptance. However, there are associated penalties with serial scan. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today's very high speed designs with minimum possible combinational depth, the performance degradation caused by scan multiplexer has became magnified. Hence to maintain the circuit performance the timing overhead of scan design must be addressed. In this paper we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer off the functional path. The proposed design can help in improving the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in mixed mode scan test wherein it can be used as a serial scan cell as well as random access scan RAS) cell.

The demand for high performance system-on-chips (SoC) in communication and computing has been growing continuously. To meet the performance goals, very aggressive circuit design techniques such as the use of smallest possible logic depth are being practiced. Replacement of normal flip-flops with scan flip-flops adds an additional multiplexer delay to critical path. Furthermore as the combinational depth decreases, the performance degradation caused by scan multiplexer delay become more critical. Elimination of the scan multiplexer delay off the functional path has become crucial in maintaining the circuit performance. In this work we propose a new transistor level scan cell design to eliminate the scan multiplexer off the functional path. The proposed scan cell uses separate master latch for functional and test mode where as the slave latch is same in both the modes. Our proposed scan flip-flop fully comply with the conventional test flow. Post layout experimental results justify the effectiveness of the proposed scan cell design in eliminating the performance penalty of scan, and thus in improving the timing performance of integrated circuits.

Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells are propagated to the combinational circuit, which inturn create many more toggling activities in the combinational block and hence increases the dynamic power consumption. The dynamic power consumed during scan shift operation is much more higher than that of normal mode operation. Due to change in design characteristic the dynamic power dissipated during scan operation becomes an important issue. The average power and peak power are the standard metric to measure dynamic power. During scan test both average power and peak power are required to be within the specified power budget for safe testing of chip. Average power causes excessive heat dissipation where as peak power causes IR drop and cross talk problem. Particularly, the excessive peak power during test-cycle of at-speed testing is vulnerable. The excessive peak power causes high rate of current in the power and ground rails which decreases the supply voltage and causes ground bounce, this phenomenon is known as IR-drop. The larger IR-drop means the worse speed performance of circuit. This degradation in performance grows if circuit is operated at high frequency which is the case during at-speed testing. This degradation in performance leads to incorrect capture of responses and this results in to undesired yield loss. Hence, to avoid yield loss the the peak power minimization is necessary especially in case of narrow test-cycle. More over the minimization of peak power is also advantageous for parallel testing of multiple core to reduce test time. In this work we have focused on the problem of peak power consumption during test-cycle for at-speed testing. The methodology proposed in this work is based on scan cells reordering. Many direction has been explored to reduce peak power during test-cycle. One of the methodology on scan reordering is proposed by Bonhomme et al. The methodology is formulated as a global optimization problem and solved using simulated annealing approach. Although the simulated annealing can provides near optimal solution if it is allowed to run for sufficient number of iteration the graph theoretic formulation will wider the solution space for scan reordering methodology. With this motivation we are proposing a graph theoretic formulation for scan reordering methodology to minimize peak power during test-cycle. The overall approach consists of graph theoretic problem formulation and an algorithm to solve it. From given scan related informations viz. scan cells, possible scan path, and power consumption a complete vector-weighted graph is constructed. The vector-weight is a weight of an edge which keeps the information of peak power consumed by each test vector. On this graph a TSP (Travelling Sales Person) problem is formulated. The cost function in this formulation is peak power. The problem formulated is NP-complete. As the problem is NP-complete we have proposed a greedy based heuristic to solve it. The proposed heuristic consists of two parts. Part 1 to find a Hamiltonian cycle which consume less peak power from the constructed complete graph and Part 2 to find a Hamiltonian path having lower peak power from Hamiltonian cycle. The Part 1 of algorithm runs in polynomial time and the Part 2 runs in linear time. The memory space required to execute these algorithms is also linear. The experiment conducted on ITC99 and ISCAS89 benchmarks show that the proposed methodology is able to reduce appreciable percentage (around 55%) of peak power compared to. Overall, this paper has proposed a novel way of formulating a graph theoretic problem for scan reordering to minimize test-cycle peak power. The scan reordering methodology may incur nominal area overhead in terms of routing and may alter the delay fault coverage for at-speed skewed-load testing. In this work we have not taken these parameters into account. However, the proposed methodology can be extended to consider these parameters. One limitation of the scan reordering methodology is it is pattern dependent. If some additional pattern has to be added on top of the existing patterns the methodology will not be able to reduce peak power effectively. This issue needs further examination.

Scan circuit testing generally causes excessive switching activity compared to normal circuit operation. This excessive switching activity causes high peak and average power consumption. Higher peak power causes, supply voltage droop and excessive heat dissipation. This paper proposes a scan cell reordering methodology to minimize the peak power consumption during scan shift operation. The proposed methodology first formulate the problem as graph theoretic problem then solve it by a linear time heuristic. The experimental results show that the methodology is able to reduce up to 48% of peak power in compared to the solution provided by industrial tool.

Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power, below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%.