Key-value stores have become pivotal in the management of data for modern large-scale data centers. Unlike the log-structured merge (LSM) tree, the Bε tree enhances read performance by mitigating read amplification and by leveraging the temporal locality of keys in the buffer area of its internal nodes. However, its inability to fully harness the high parallelism of solid-state drives (SSDs) limits its effectiveness. This limitation stems from traditional SSDs concealing their parallelism from the host system. The advent of open-channel SSDs (OCSSDs), which expose the physical data storage layout to the host system, provides a unique opportunity to leverage SSDs' inherent high parallelism in read/write operations. This paper introduces a novel high-parallelism Bε (HP-Bε) indexing scheme designed for OCSSDs. The scheme specifically addresses conflicts between parallel units (PUs) during read operations, substantially improving read performance of the Bε indexing approach. To our knowledge, this is the first study to adapt the Bε indexing scheme for the OCSSD architecture, and our experimental results are promising.

The Bϵ tree is an essential indexing structure in modern file and database systems, renowned for its high read and write performance. However, constructing a Bε tree involves substantial write overhead due to repetitive key writing during flushing. This study presents the mw-Bϵ tree, a novel approach leveraging multi-write modes in persistent memory to reduce Bϵ tree construction costs. By dynamically adapting write modes based on node update frequencies, the mw-Bϵ tree outperforms traditional fixed-mode indexing schemes. Our research demonstrates that integrating multi-write mode support in non-volatile memory (NVM) can significantly enhance the efficiency of Bϵ tree indexing. Experimental results using real-world workloads show that the mw-Bε tree reduces power consumption by up to 43.5% and energy usage by 27.6%, while also improving write latency. This work is the first to investigate and address power consumption challenges in Bε tree construction, providing a compelling case for the adoption of multi-write modes in NVM technologies for indexing structures.

During the unprecedented expansion of global data, efficient storage solutions are essential for processing massive datasets stored on modern storage devices. B-epsilon-tree (Bε-tree) is one of the most well-known techniques that provides a write-optimized structure for database file systems. With the excellent access performance and high energy efficiency of solid-state drives (SSDs), they are expected to yield promising outcomes for large-scale data computation. However, their integration into storage systems has the challenges of write amplification, which impacts SSD endurance and reliability. This work identifies significant write amplification issues with Bε-tree implementations on SSDs due to the complicated management of key-value pairs. To mitigate the impact of write amplification, we propose PULSE, a novel scheme that rethinks Bε-tree designs by leveraging log-structured techniques optimized for SSDs. Moreover, PULSE integrates auxiliary indexing and a dual flush selector to minimize write amplification. Experimental results demonstrate that PULSE significantly mitigates write amplification by more than 62.6% on SSDs for the representative benchmarks compared to the Bε-tree.

Due to the prevalence of social network applications and graph database systems, large-scale graphs have become a mainstream data structure for data mining and machine learning. However, the challenge arises from the limited size of dynamic random-access memory (DRAM), preventing the simultaneous processing of entire large-scale graphs in modern computer systems. Consequently, the need arises to partition the overall large-scale graph into multiple sub-graphs for parallel processing and to align with available computing resources. Unfortunately, existing graph partitioning solutions do not adequately address the load/store overhead on the storage device during the partitioning process. As the graph partitioning process involves finding the optimal splitting edge to ensure sub-graph balance and preserve the original properties of the large-scale graph, there is frequent loading from and storing to the storage device. This issue is further exacerbated on NAND flash memory due to its basic read/write unit (i.e., a page size). This paper introduces GraLoc, a graph partitioning solution designed to be NAND flash memory-friendly by considering graph locality during data placement. The proposed solution aims to maximize graph locality within a single page, effectively minimizing read amplification during the graph partitioning process. Our experiments demonstrate a significant improvement in storage performance during graph partitioning.

In key-value store systems, data security is often prioritized through compression and encryption of stored key-value pairs, ensuring protection against unauthorized access and breaches. However, these security measures introduce significant performance overheads, particularly during read operations, due to the need for decryption and decompression of data packs. This overhead is exacerbated in log-structured merge-tree (LSM-tree) based systems interfaced with NAND flash memory, where read amplification—caused by accessing entire compressed and encrypted units for a small subset of data—degrades performance. To address this challenge, we propose ReLoaD (Repacking Locality Data), a novel locality-based strategy designed to optimize read performance in encrypted key-value systems without compromising security or compression efficiency. ReLoaD leverages dynamic access pattern analysis to reorganize frequently co-accessed key-value pairs into contiguous storage packs, reducing the frequency of costly decryption and decompression operations. By introducing lightweight in-memory data structures—such as the PackInfo and Remapthl mapping tables—and innovative mechanisms like the locality-aware compactor and reloading repacker, ReLoaD enhances data locality within packs, minimizes I/O overhead, and increases the pack read ratio. Experimental evaluations using real-world workloads from X (formerly known as Twitter) and IBM, executed on the RocksDB platform, demonstrate that ReLoaD achieves up to a 38% improvement in read latency compared to state-of-the-art solutions like TinyEnc, while maintaining minimal impact on write performance. With a memory footprint of less than 3 MB, ReLoaD offers a scalable and practical approach to balancing security and performance, making it well-suited for modern secure storage systems deployed in resource-constrained environments.

High-density NAND flash has revolutionized the storage ecosystem because of its rapidly decreasing per-bit costs and unprecedented capacities. However, the inherent large block size of modern high-density NAND flash inevitably aggravates the reclamation latency (i.e., the time required to reclaim the storage space occupied by the obsolete data), which subsequently prolongs the tail latency of flash-based storage devices. Inspired by the “erase duality” from the emerging bit-alterable NAND flash, this article proposes a reclamation latency suppressed (RLS) space management design to synergize the strengths of both block-level erase and page-level erase. Taking into account the data update frequency during runtime, RLS enables proactive adjustment of the dual-granularity erase. Moreover, RLS tightly couples the data cluster allocation strategy with a novel dual-granularity space reclamation design, thereby alleviating the reclamation latency. We extensively examine the benefits of RLS with real-world workloads. Our evaluation results reveal that, with the suppressed space reclamation latency, RLS achieves up to 37.51% improvement for both write and read tail latency (latency at the 99.9th percentile) compared with the state-of-the-art approaches.

Due to the exponential growth of data in computing, DRAM-based main memory is now insufficient for data-intensive applications like machine learning and recommendation systems. This has led to a performance issue involving data transfer between main memory and storage devices. Conventional NAND-based SSDs are unable to efficiently handle this problem as they can't distinguish between data types from the host system. In contrast, open-channel SSDs (OCSSD) offer a solution by optimizing data placement from the host-side system. This research focuses on developing a new data access model for deep learning recommendation systems (DLRM) using OCSSD storage drives, called OC-DLRM. OC-DLRM reduces I/O traffic to flash memory by aggregating frequently-accessed data using the I/O unit of a flash memory drive. Our experiments show that OC-DLRM has significant performance improvement compared with traditional swapping space management techniques.

This work discovers a flash memory performance issue resulting from flash superpages organization. Because of process variation, each flash page has its own read/write performance. If a slow page is grouped with a fast page in a superpage unit, computer systems with solid-state drives (SSD) receive a poor performance result. In this work, we prove the existence of this issue by conducting a series of experiments on a real SSD platform. To resolve this issue, we characterize flash memory chips to find hints to organize super-fast superpages in SSDs. By the tips, this work develops a process-variation check scheme (PV Check) that can group a superpage with an optimized performance at runtime with low overheads. According to our experiments, the PV Check scheme has encouraged results in performance improvement. Compared with a traditional method, our work can decrease the extra program and erase latency by 16.61% and 34.55%, respectively.

Skyrmion racetrack memory (SK-RM) has demonstrated great potential as a high-density and low-cost nonvolatile memory. Nevertheless, even though random data accesses are supported on SK-RM, data accesses can not be carried out on individual data bit directly. Instead, special skyrmion manipulations, such as injecting and shifting, are required to support random information update and deletion. With such special manipulations, the latency and energy consumption of skyrmion manipulations could quickly accumulate and induce additional overhead on the data read/write path of SK-RM. Meanwhile, injection operation consumes more energy and has higher latency than any other manipulations. Although prior arts have tried to alleviate the overhead of skyrmion manipulations, the possibility of minimizing injections through buffering skyrmions for future reuse and energy conservation receives much less attention. Such observation motivates us to propose the concept of skyrmion vault to effectively utilize the skyrmion buffer track structure for energy conservation through maximizing the lifespan of injected skyrmions and minimizing the number of skyrmion injections. Experimental results have shown promising improvements in both energy consumption and skyrmions' lifespan.

This study investigates non-CS major students' performance in computer programming and Information Technology-integrated (IT I) courses at a Taiwanese research university. Non-CS students struggle in introductory programming due to syntax and logical thinking limitations, resulting in lower grades compared to advanced programming. Similarly, ITI course grades are lower due to subject-specific demands. Gender and entry channels impact outcomes, with females excelling in informal learning. Favorable results are seen in individual applications and Multi-star Projects. Challenges include different learning paces and cultural adjustments. Regression analysis shows Introduction to Computer Programming (ICP), Advanced Computer Programming (ACP) and gender significantly affect ITI performance, explaining 24% of its variance. Recommendations include diverse teaching methods, problem-solving guidance, practical programming, collaboration, and project participation to enhance skills.

The continuous increase in data volume has led to the adoption of shingled-magnetic recording (SMR) as the primary technology for modern storage drives. This technology offers high storage density and low unit cost but introduces significant performance overheads due to the read-update-write operation and garbage collection (GC) process. To reduce these overheads, data deduplication has been identified as an effective solution as it reduces the amount of written data to an SMR-based storage device. However, deduplication can result in poor data locality, leading to decreased read performance. To tackle this problem, this study proposes a data locality-aware deduplication technology, LaDy, that considers both the overheads of writing duplicate data and the impact on data locality to determine whether the duplicate data should be written. LaDy integrates with DiskSim, an open-source project, and modifies it to simulate an SMR-based drive. The experimental results demonstrate that LaDy can significantly reduce the response time in the best-case scenario by 87.3% compared with CAFTL on the SMR drive. LaDy achieves this by selectively writing duplicate data, which preserves data locality, resulting in improved read performance. The proposed solution provides an effective and efficient method for mitigating the performance overheads associated with data deduplication in SMR-based storage devices.

Process variation in the 3D flash memory architecture raises the difficulty of bad block management. Since the error characteristics vary among different blocks, it is difficult for the existing P/E cycle-based bad block management policies to decide a suitable cycle threshold. This increases the possibility of data loss and decreases the SSD’s lifetime. In this work, we characterize the 3D flash memory and observe spatial correlation among flash blocks in the aspect of error behaviors. This phenomenon is referred to as cluster similarity. A novel cluster-based bad block management policy is proposed, which treats the failure of a block as an indicator of near-future failures of its neighboring blocks. Moreover, we provide quantitative methods to enable judicious selection of the cluster size to meet the desired tradeoff between the SSD lifetime and reliability. Compared with the commonly-used cycle-based bad block management policy, our cluster-based management policy has a lifetime improvement of 2x with comparable failure rates. And with comparable lifetime, the failure rate of the cycle-based policy is 9x higher than our method. To alleviate the I/O performance impact caused by the cluster retirement, we proposes a critical-block first reallocation scheduling. Our experiments show up to two times improvement of the 95th percentile latency compared to the naive scheduling of cluster reallocation.

Many prior research works have been widely discussed how to bring machine learning algorithms to embedded systems. Because of resource constraints, embedded platforms for machine learning applications play the role of a predictor. That is, an inference model will be constructed on a personal computer or a server platform, and then integrated into embedded systems for just-in-time inference. With the consideration of the limited main memory space in embedded systems, an important problem for embedded machine learning systems is how to efficiently move inference model between the main memory and a secondary storage (e.g., flash memory). For tackling this problem, we need to consider how to preserve the locality inside the inference model during model construction. Therefore, we have proposed a solution, namely locality-aware random forest (LaRF), to preserve the inter-locality of all decision trees within a random forest model during the model construction process. Owing to the locality preservation, LaRF can improve the read latency by 81.5% at least, compared to the original random forest library.

Bit-alterable flash memory is a cutting-edge technology that enables a novel operation, called page-level erase operation, to erase a flash page within a block arbitrarily. Though the page-level erase operation can ease the overhead of the live-page copying during a garbage collection process, it also introduces a new wear-leveling problem. In such the problem, flash pages within the same block will receive different program/erase (P/E) cycles during runtime. Some specific pages storing hot data will be worn out soon; therefore, the lifespan of the bit-alterable flash memory will be short due to the uneven worn out of flash pages. Consequently, it becomes a critical issue with the bit-alterable flash memory, and the state-of-art wear-leveling designs cannot resolve this problem. For tackling the problem, this study presents a duo-phase data management scheme considering the page-level wear-leveling issue. The duo-phase mechanism simultaneously cares about page- and block-level wear-leveling issues. On the page-level wear-leveling problem, the duo-phase scheme identifies hot flash pages via the few bits and softly restricts the hot flash page to store hot data. On the other hand, our proposed mechanism also figures out the solution to minimize the number of copied live pages for the block-level wear-leveling issue.

Because of large cell density, fast read/write performance, and no limited write cycles, magnetic skyrmion racetrack memory (SK-RM) has been regarded as the next-generation main memory technology. However, the characteristics of SK-RM are not friendly for a B+-tree indexing structure that is widely applied to database and file systems because some B+-tree structure’s operations (including splitting, merging, and query) need to reproduce skyrmion elements for copying keys and repeatedly shift skyrmion elements to access ports for a binary search operation. In this work, we elaborate on the overheads of establishing a B+-tree structure on the SK-RM architecture. To eliminate the overhead, this work proposes a skyrmion-friendly B+-tree structure, namely Sky-tree, that fully exploits the benefits of the SK-RM architecture by a bit-level binary search method, node-based skyrmion recycler, and an intratrack node splitting strategy. The design principle of the skyrmion-friendly B+-tree is to minimize the number of generated skyrmion elements and the shift overhead per query operation. The experimental results show that our skyrmion-friendly B+-tree structure can improve the performance by up to 78%, compared with a baseline solution.

The advancement of nonvolatile memory (NVM) technology reduces the cost-per-unit of solid-state drives (SSDs). Flash memory-based SSDs have become ubiquitous because they provide better performance and energy efficiency than hard disk drives. However, it suffers from wear-out problems caused by the out-of-place updates that limit its lifetime. Log-structured merge tree (LSM-tree) is a level-based data structure that is widely used in many database systems because it eliminates the random write operations to the storage devices. By transferring the random write operations into sequential write operations, the write performance of hard disk drives can be improved. However, LSM-tree is not efficient for SSDs because it is not aware of the access characteristics of flash memory. Moreover, the level-based indexing strategy of the LSM-tree significantly shortens the lifetime of SSDs because the data must be frequently updated due to the compaction operations between different levels. In contrast to many previous works that focus on alleviating the write amplification on SSDs for the database systems implemented by LSM-tree, we propose LLSM, a lifetime-aware wear-leveling for LSM-tree on NAND flash memory with open-channel SSD. By considering the data access frequency of the LSM-tree between different levels, LLSM rethinks the block allocation strategy during the compaction to evenly erase all the blocks of SSD storage devices, prolonging the SSD lifetime. Moreover, a proactive swapping strategy is designed to reorganize the data blocks for resolving the potential wear-leveling issues caused by the behaviors of the LSM-tree. The extensive experiments show that the results of lifetime improvement are encouraging.

Recently, the requirement of storing digital data has been growing rapidly; however, the conventional storage medium cannot satisfy these huge demands. Fortunately, thanks to biological technology development, storing digital data into deoxyribonucleic acid (DNA) has become possible in recent years. Furthermore, because of the attractive features (e.g., high storing density, long-term durability, and stability), DNA storage has been regarded as a potential alternative storage medium to store massive digital data in the future. Nevertheless, reading and writing digital data over DNA requires a series of extremely time-consuming processes (i.e., DNA sequencing and DNA synthesis). More specifically, among the two costs, the writing cost is the predominant cost of a DNA data storage system. Therefore, to enable efficient DNA storage, this article proposes an index management scheme for reducing the number of accesses to DNA storage. Additionally, this article introduces a new DNA data encoding format with VERA (Version Editing Recovery Approach) to reduce the total writing bits while inserting and deleting the data. To the best of our knowledge, this work is the first work to provide a total data management solution for DNA storage. According to the experimental results, the proposed design with VERA can reduce the cost by 77% and improve the performance by 71% compared to the append-only methods.

Random forest has been widely used to classifying objects recently because of its efficiency and accuracy. On the other hand, nonvolatile memory has been regarded as a promising candidate to be a part of a hybrid memory architecture. For achieving the higher accuracy, random forest tends to construct lots of decision trees, and then conducts some post-pruning methods to fell low contribution trees for increasing the model accuracy and space utilization. However, the cost of writing operations is always very high on non-volatile memory. Therefore, writing the to-be-pruned trees into non-volatile memory will significantly waste both energy and time. This work proposed a framework to ease such hurt of training a random forest model. The main spirit of this work is to evaluate the importance of trees before constructing it, and then adopts different writing modes to write the trees to the non-volatile memory space. The experimental results show the proposed framework can significantly mitigate the waste of energy with high accuracy.

Intermittent systems enable continuous and accumulative process execution under constraint or unstable power supply. To enable intermittent computing, process status and data are typically checkpointed from volatile memory (VM) to nonvolatile memory (NVM) before running out of power. After power resumes, these logged data can be loaded back from NVM to VM for continuous execution. Nevertheless, existing approaches rarely considered the energy consumed during moving data and may waste precious power resource over data movement, instead of computation. Such observation motivates us to propose an energy-reduction on-chip memory management (ERCM2) scheme to utilize the high cell density and non-volatility of SpinTransfer Torque RAM (STT-RAM) for enabling a hybrid on chip memory architecture. The experimental results show that the proposed scheme can achieve the access performance close to conventional SRAM-based on-chip memory architecture with lower energy consumption.

Recently, nonvolatile random-access memory (NVRAM) has been regarded as the most up-and-coming main memory technology in embedded and Internet-of-Things (IoT) systems due to its attractive features: zero-static power consumption and high memory cell density. However, the endurance issue as a “nightmare” always haunts NVRAM system developers. Worse still, NVRAM’s lifespan will wear out soon in embedded applications because their data management systems usually utilize an indexing scheme to maintain small data. Plus, a node structure within the indexing scheme will be frequently updated because of data creation and deletion. Therefore, many previous works rethink B+-tree indexing scheme on an NVRAM-based system. The most previous studies focused on reducing the amount of write traffic to memory. Unfortunately, they are failed to extend the NVRAM lifespan because their solution cannot evenly distribute the amount of write traffic to each memory cell. Additionally, prior solutions have not considered that all nodes within B+-tree indexing structure have different update frequencies. Based on such the observation, this work proposes a wear-leveling-aware B+-tree design, namely, waB+-tree, to consider the update frequency of each node within the B+-tree structure, so as to evenly scatter the amount of write traffic to the NVRAM cells. According to our experiments, the proposed waB+-tree shows the encouraging results of endurance improvement.

Due to cyber-physical systems, a large-scale multiversion indexing scheme has garnered significant attention in recent years. However, modern multiversion indexing schemes have significant drawbacks (e.g., heavy write traffic and weak key- or version-range-query performance) while being applied to a computer system with a nonvolatile random access memory (NVRAM) as its main memory. Unfortunately, with the considerations of high memory cell density and zero-static power consumption, NVRAM has been regarded as a promising candidate to substitute for dynamic random access memory (DRAM) in future computer systems. Therefore, it is critical to make a multiversion indexing scheme friendly for an NVRAM-based system. For tackling this issue with modern multiversion indexing schemes, this article proposes a write-reduction multiversion indexing scheme with efficient dual-range queries. According to the experiments, our scheme effectively reduces the amount of write traffic generated by the multiversion indexing scheme to NVRAM. It offers efficient dual-range queries by consolidating the proposed version forest and the multiversion tree.

Owing to the explosive growth of data volume, high areal density storage technologies have been proposed in the past few years. Among them, shingled magnetic recording (SMR) has been regarded as the most promising candidate to replace current conventional hard disk drive based on the perpendicular magnetic recording technology. However, SMR technology not only brings large capacity storage devices but also results in terrible random access performance. For increasing the random access performance of SMR, solid-state hybrid drive (SSHD) seems a possible solution in storage system development. Nevertheless, when an SMR-based SSHD is adopted to a large-scale data management system, a severe performance degeneration will happen because an indexing scheme for access efficiency always maintains data in the large-scale data management system. More specifically, jointly managing indexing keys and data values on an SSHD drive will result in the massive amount of write amplification because of read-merge-write operations and garbage collection processes. Based on such motivations, this work proposed a total solution, namely XsB+-tree, to establish a high-performance B+-tree-based data management scheme for key-value store systems. To the best of our knowledge, this work is the first work to discuss the total solution for the key-value store over an SMR-based SSHD. According to our experimental results, XsB+-tree can improve the access time by 80% on average and prolong the lifetime of SSD up to 19%.

Owing to flash memory constraints, a garbage collection (GC) mechanism hurts flash storage lifespan and performance since it generates a massive amount of write data to flash memory. To add insult to injury, all GC designs cannot identify disused data from valid data; therefore, all valid data, including disused data, will be rewritten to flash memory during the GC process. Fortunately, a flash storage vendor recently proposed a new write command to bring extra information to flash translation layer (FTL). Thanks to the new write command, the lifetime information of data can be brought from a host-side system to an FTL management layer for disused data identification. By such observations, this work proposes a dual-time referencing FTL (DTR-FTL) design to deal with disused data and minimize the overhead of GC by referring to data lifetime information and block retention time.

Decision tree is the core algorithm of the random forest learning that has been widely applied to classification and regression problems in the machine learning field. For avoiding underfitting, a decision tree algorithm will stop growing its tree model when the model is a fully-grown tree. However, a fully-grown tree will result in an overfitting problem reducing the accuracy of a decision tree. In such a dilemma, some post-pruning strategies have been proposed to reduce the model complexity of the fully-grown decision tree. Nevertheless, such a process is very energy-inefficiency over an non-volatile-memory-based (NVM-based) system because NVM generally have high writing costs (i.e., energy consumption and I/O latency). Such unnecessary data will induce high writing energy consumption and long I/O latency on NVM-based architectures, especially for low-power-oriented embedded systems. In order to establish a green decision tree (i.e., a tree model with minimized construction energy consumption), this study rethinks a pruning algorithm, namely duo-phase pruning framework, which can significantly decrease the energy consumption on the NVM-based computing system without loss of accuracy.

Nonvolatile random access memory (NVRAM) is becoming a popular alternative as the memory and storage medium in battery-powered embedded systems because of its fast read/write performance, byte-addressability, and nonvolatility. A well-known example is phase-change memory (PCM) that has much longer life expectancy and faster access performance than NAND flash. When NVRAM is considered as both main memory and storage in battery-powered embedded systems, existing page cache mechanisms have too many unnecessary data movements between main memory and storage. To tackle this issue, we propose the concept of “union page cache,” to jointly manage data of the page cache in both main memory and storage. To realize this concept, we design a partial page cache strategy that considers both main memory and storage as its management space. This strategy can eliminate unnecessary data movements between main memory and storage without sacrificing the data integrity of file systems. A series of experiments was conducted on an embedded platform. The results show that the proposed strategy can improve the file accessing performance up to 85.62% when PCM used as a case study.

Nonvolatile random access memory (NVRAM) has been regarding a promising technology to replace DRAM as the main memory in embedded systems owing to its nonvolatility and low idle power consumption. However, due to the asymmetric read/write costs and limited lifetime of NVRAM, most of the existing fundamental algorithms are not NVRAM-friendly with their write pattern and write intensiveness. Thus, existing fundamental algorithms for NVRAM embedded devices has been revealed. For instance, as the sorting algorithm is one of the most fundamental algorithms, most of the existing sorting algorithms are not NVRAM-friendly because they impose heavy write traffic [i.e., O(n lgn)] on main memory, where n is the number of unsorted elements. To resolve this issue, this article proposes a write-once sorting algorithm, namely B*-sort, to reduce the amount of write traffic on NVRAM-based main memory. B*sort adopts a brand-new concept, i.e., tree-based sort, inspired by the binary-search-tree structure to achieve the write-once property which can guarantee the optimal endurance during the sorting process. According to the experimental results, B*-sort can achieve significant performance improvement for sorting on NVRAM-based systems.

To meet the requirement of low-power consumption, multi-level-cell STT-RAM (MLC STT-RAM) has been widely regarded as a potential candidate for replacing DRAM-based main memory in the next generation computer architectures because of its high memory cell density, fast read/write performance and zero refresh power consumption. However, MLC STT-RAM has higher power consumption than DRAM while a write operation is performed because MLC STT-RAM sometimes needs to perform a two-step transition to change the originally stored bits to another specifically written bit patterns. As a result, MLC STT-RAM has different power consumption while different bit patterns are written to a memory cell. To the best of our knowledge, a few or none of the previous studies rethink a cache replacement policy to overcome the asymmetric write energy issue of MLC STT-RAM-based main memory. Thus, this study proposes an energy-aware cache replacement policy, namely E-cache, which considers asymmetric write-back power consumption on MLC STT-RAM-based main memory to evict a proper cached data from the last-level cache, so as to minimize system power consumption. The experimental results show that the proposed solution reduces the energy consumption by 36% on average, compared with the LRU.

Growing demand for key-value store applications is building a strong momentum for the commercialization of key-value hard disk drives. To achieve better performance, flash-based solid state drive is the next ideal candidate for commercialization in the foreseeable future. However, the existing fixed-sized management strategies of flash-based devices would potentially result in low storage space utilization when managing variable-sized key-value data. In addition, the low storage space utilization would further lead to the degradation of device performance, due to low invalid data space reclamation efficiency. The space utilization issue motivates this paper to propose a key-value flash translation layer design to improve storage space utilization as well as the performance of the key-value solid state drives. A series of experiments was conducted to evaluate the proposed design, and the experiment results of space utilization and device performance are very encouraging.

When a shingle magnetic recording (SMR) drive has been widely applied to modern computer systems (e.g., archive file systems, big data computing systems, and large-scale database systems), storage system developers should thoroughly review whether current designs (e.g., index schemes and data placements) are appropriate for an SMR drive because of its sequential write constraint. Through many prior works excellently manage data in an SMR drive by integrating their proposed solutions into the driver layer, an index scheme over an SMR drive has never been optimized by any previous works because managing index over the SMR drive needs to jointly consider the properties of B + -tree and SMR natures (e.g., sequential write constraint and zone partitions) in a host storage system. Moreover, poor index management will result in terrible storage performance because an index manager is extensively used in file systems and database applications. For optimizing the B + -tree index structure over an SMR storage, this work identifies performance overheads caused by the B + -tree index structure in an SMR drive. By such observation, this study proposes a sequential-write-constrained B + -tree index scheme, namely SW-B + tree, which consists of an address redirection data structure, an SMR-aware node allocation mechanism, and a frequency-aware garbage collection strategy. According to our experiments, the SW-B + tree can improve the SMR storage performance 55% on average.

Due to the fast access performance, byte-addressability, and non-volatility of non-volatile random access memory (NVRAM), NVRAM has emerged as a popular candidate for the design of memory/storage systems on mobile computing systems. For example, the latest 3D xPoint memory could be a kind of NVRAM with much longer life expectancy than NAND flash and could ease the possible endurance issue. When NVRAM is considered as both main memory and storage in mobile computing systems, existing page cache mechanisms introduce too many unnecessary data movements between main memory and storage. To resolve this issue, we propose the concept of "union page cache," which jointly manages data of the page cache in both main memory and storage. To realize this concept, a partial page cache strategy is designed to consider both main memory and storage as its management space and to eliminate unnecessary data movements between main memory and storage without sacrificing the data consistency of file systems. Experimental results show that the proposed strategy can boost the file accessing performance upto 85.62% when using PCM as a case study.

Due to the decreasing endurance of flash chips, the lifetime of flash drives has become a critical issue. To resolve this issue, various techniques such as wear-leveling and error correction code have been proposed to reduce the bit error rates of flash storage devices. In contrast to these techniques, we observe that minimizing write amplification is another promising direction to enhance the lifetime of a flash storage device. However, the development trend of large-page flash memory exacerbates the write amplification issue. In this work, we present a compression-based management design to deal with compressed data updates and internal fragmentation in flash pages. Thus, it can minimize write amplification by only updating the modified part of flash pages with the support of data reduction techniques; and the reduced write amplification degree is more significant when the flash page size becomes larger due to the development trend. This design is orthogonal to wear-leveling and error correction techniques and thus can cooperate with them to further enhance the lifetime of a flash device. Based on a series of experiments, the results demonstrate that the proposed design can effectively improve the lifetime of a flash storage device by reducing write amplification.

Non-volatile random-access memory (NVRAM) is regarded as a great alternative storage medium owing to its attractive features, including low idle energy consumption, byte addressability, and short read/write latency. In addition, multi-level-cell (MLC) NVRAM has also been proposed to provide higher bit density. However, MLC NVRAM has lower energy efficiency and longer write latency when compared with single-level-cell (SLC) NVRAM. These drawbacks could lead to higher energy consumption of MLC NVRAM-based storage systems. The energy consumption is magnified by existing journaling file systems (JFS) on MLC NVRAM-based storage devices due to the JFS's fail-safe policy of writing the same data twice. Such observations motivate us to propose a multi-write-mode journaling file systems (mwJFS) to alleviate the drawbacks of MLC NVRAM and lower the energy consumption of MLC NVRAM-based JFS. The proposed mwJFS differentiates the data retention requirement of journaled data and applies different write modes to enhance the energy efficiency with better access performance. A series of experiments was conducted to demonstrate the capability of mwJFS on a MLC NVRAM-based storage system.

Non-volatile random-access memory (NVRAM) becomes a mainstream storage device in embedded systems due to its favorable features, such as small size, low power consumption, and short read/write latency. Unlike dynamic random access memory (DRAM), NVRAM has asymmetric performance and energy consumption on read/write operations. Generally, on NVRAM, a write operation consumes more energy and time than a read operation. Unfortunately, current mobile/embedded file systems, such as EXT2/3 and EXT4, are very unfriendly for NVRAM devices. The reason is that current mobile/embedded file systems employ a journaling mechanism for increasing its data reliability. Although a journaling mechanism raises the safety of data in a file system, it also repeatedly writes data to a data storage while data is committed and checkpointed. Though several related works have been proposed to reduce the amount of write traffic to NVRAM, they still cannot effectively minimize the write amplification of a journaling mechanism. Such observations motivate us to design a two-phase write reduction journaling file system called wrJFS. In the first phase, wrJFS classified data into two categories: Metadata and user data. As the size of metadata is usually very small (few bytes), byte-enabled journaling strategy will handle metadata during commit and checkpoint stages. In contrast, the size of user data is very large relative to metadata; thus, user data will be processed in the second phase. In the second phase, user data will be compressed by hardware encoder to reduce the write size and managed compressed-enabled journaling strategy to avoid the write amplification on NVRAM. Moreover, we analyze the overhead of wrJFS and show that the overhead is negligible. According to the experimental results, the proposed wrJFS outperforms other journaling file systems even though the experiments include the overhead of data compression.

Owing to high cell density caused by the advanced manufacturing process, the reliability of flash drives turns out to be rather challenging in flash system designs. To enhance the reliability of flash drives, error-correcting code (ECC) has been widely utilized in flash drives to correct error bits during programming/reading data to/from flash drives. Although ECC can effectively enhance the reliability of flash drives by correcting error bits, the capability of ECC would degrade while the program/erase (P/E) cycles of flash blocks is increased. Finally, ECC could not correct a flash page, because a flash page contains too many error bits. As a result, reducing error bits is an effective solution to further improve the reliability of flash drives when a specific ECC is adopted in the flash drive. This work focuses on how to reduce the probability of producing error bits in a flash page. Thus, we propose a pattern-aware write strategy for flash reliability enhancement. The proposed write strategy considers both the P/E cycle of blocks and the pattern of written data while a flash block is allocated to store the written data. Since the proposed write strategy allocates young blocks (respectively, old blocks) for hot data (respectively, cold data) and flips the bit pattern of the written data to the appropriate bit pattern, the proposed strategy can effectively improve the reliability of flash drives. The experimental results show that the proposed strategy can reduce the number of error pages by up to 50%, compared with the well-known DFTL solution. Moreover, the proposed strategy is orthogonal with all ECC mechanisms so that the reliability of the flash drives with ECC mechanisms can be further improved by the proposed strategy.

With the advanced technology in persistent random access memory (PRAM), PRAM such as three-dimen-sional XPoint memory and Phase Change Memory (PCM) is emerging as a promising candidate for the next-generation medium for both (main) memory and storage. Previous works mainly focus on how to overcome the possible endurance issues of PRAM while both main memory and storage own a partition on the same PRAM device. However, a holistic software-level system design should be proposed to fully exploit the benefit of PRAM. This article proposes a union storage file system (UnistorFS), which aims to jointly manage the PRAM resource for main memory and storage. The proposed UnistorFS realizes the concept of using the PRAM resource as memory and storage interchangeably to achieve resource sharing while main memory and storage coexist on the same PRAM device with no partition or logical boundary. This approach not only enables PRAM resource sharing but also eliminates unnecessary data movements between main memory and storage since they are already in the same address space and can be accessed directly. At the same time, the proposed UnistorFS ensures the persistence of file data and sanity of the file system after power recycling. A series of experiments was conducted on a modified Linux kernel. The results show that the proposed UnistorFS can eliminate unnecessary memory accesses and outperform other PRAM-based file systems for 0.2--8.7 times in terms of read/write performance.

The strong momentum of key-value store applications drives the commercialization of key-value-specific hard disk drives. To achieve higher degree of performance, the specific flash-based solid state drives would be also commercialized for key-value store applications in the foreseeable future. However, the existing fixed-sized management strategies of flash-based devices would potentially result in low storage space utilization on managing variable-sized key-value data. This problem inspires this paper to propose a key-value flash translation layer (KVFTL) design to improve the storage space utilization of the key-value-specific solid state drives (KVSSDs). A series of experiments was conducted to evaluated the proposed design, and the experimental results on space utilization and device performance are very encouraging.

As the volume of data stored by Big data and Cloud services continues to grow, both academia and industry are seeking for high-performance storage systems. Recently, with the recent advances in write-optimized indexes (WOI), WOI-based file systems can now outperform conventional file systems with orders of magnitude on random writes, metadata updates, and small file creation. Based on the B-tree structure, WOI-based file systems can not only process data faster than the conventional B-tree but also improve the range query performance. However, the write amplification of these WOI-based file systems becomes a serious performance overhead when adopting flash storage as underlying storage devices due to the recursive entry update behavior. To mitigate the write amplification problem of WOIbased file systems, we propose a flash-friendly WOI design to reduce the number of write requests on flash storage. To evaluate the performance of the proposed design, we adapt B+-tree as a case study and the experimental results are promising.

Non-volatile memory (NVM) has widely participated in the evolution of the next-generation memory architecture by way of being the substitution of the main memory. To cope with the problem of asymmetric read/write speeds of NVM, several excellent researches have been proposed to reduce the number of writes to the NVM-based main memory. Nevertheless, most of these existing approaches do not take the cache-line-based access behavior between the processor and the main memory into consideration. Thus, in order to essentially improve the access performance of the NVM-based memory architecture, this work aims to optimize the cache-line-based access performance over the NVM-based memory architecture based on the special access patterns in many popular internet of things (IoT) and in-memory database applications. Our experiments based on the well-known Gem5 full system simulator reveal that, compared to other existing representative approaches, the proposed design can effectively reduce the total execution time of insertion by 20.92~55.20% and improve the execution time of query by 2.06~23.36%.

Non-volatile random-access memory (NVRAM) becomes a mainstream storage device in embedded systems due to its favorable features, such as small size, low power consumption, and short read/write latency. On NVRAM, a write operation consumes more energy and time than a read operation. However, current mobile/embedded file systems (e.g., EXT2/3 and EXT4) are very unfriendly for NVRAM devices. The reason is that a journaling mechanism writes the same data twice during data commitment and checkpoint. Such observations motivate this paper to design a two-phase write reduction journaling file system called wrJFS. In the first phase, wrJFS classified data into two categories: Metadata and user data. Metadata will be handled by partial byte-enabled journaling strategy, and user data will be processed in the second phase. In the second phase, user data will be compressed by hardware encoder so as to reduce the write size, and managed compressed-enabled journaling strategy to avoid the write amplification. The experimental results show that the proposed wrJFS can reduce the size of the write request by 89.7% on average, compared with the original EXT3.

Since 3D NAND flash memory could provide more reliable storage than a 2D planar flash memory by relaxing the design rule of a memory cell, a kind of brand new programming technique, namely erase-free scheme, has been proposed to further enhance the endurance of a 3D SLC NAND flash memory. The erase-free scheme brings tons of benefits to flash memory performance and endurance. For example, the erase-free scheme could reclaim invalid (page) space without physically erasing a flash block. However, current flash management designs could not fully exploit the benefits of the erase-free scheme. With the considerations of the features of the erase-free scheme, this paper is the first work to propose a novel flash management design, namely VirtualGC strategy, to deal with the erase-free garbage collection process. By taking the advantages of the erase-free scheme, the proposed strategy reduces the overhead of copying live pages so as to increase flash memory performance. The results show that the proposed strategy significantly improves the performance of rewritable 3D flash memory drives.

In our previous work, a simulation framework was proposed to focus on imitating the behavior of wireless charging vehicles (WCVs) and wireless sensor networks (WSNs) because current mainstream simulators have very limited support on simulation of WCVs. The WCV is an integration of a mobile vehicle and a wireless power transfer broadcaster, which is used to recharge sensors wirelessly to prolong the lifetime of sensor networks. In the study of WCVs, simulators are extensively used to study the routing algorithms and behaviors of WCVs because it is very costly to build a WSN testbed and many specifications are not standardized. However, mainstream WSN simulators require researchers to develop and integrate their WCV modules. Therefore, the previously proposed framework aims to provide a simple framework for simulating of wireless power transfer and mobile vehicles. In this study, to further strength the usability of the proposed simulation framework, a graphic user interface is introduced to allow users to assign sensors' location and specify simulation parameters.

To accommodate the sheer volume of data in the era of Big Data and Cloud Computing, both new storage medium technologies and high-performance file systems are proposed. For storage medium, Shingled Magnetic Recording (SMR) increases the areal density by overlapping adjacent tracks so as to provide larger storage capacity. On the other hand, write-optimized indexes (WOI) file systems are also studied and can now outperform conventional file systems with orders of magnitude. However, the main drawback of SMR is the random-write restriction because random-write operations will cause the extra overhead of rewriting data stored in overlapped tracks. The rewriting overhead is amplified by the recursive entry update behavior of WOI-based file systems. Therefore, the rewriting issue becomes a serious performance overhead when adopting SMR drives as underlying storage devices for WOI-based file systems. To mitigate the write amplification problem when deploying WOI-based file systems on SMR disks, this paper proposes the update-overhead-aware caching policy to reduce the update overhead with the help of flash-based storage devices. To evaluate the performance of the proposed design, the B+-tree as a case study. The experimental results are promising.

Since the mid-2000s, mobile/embedded computing systems conventionally have limited computing power, Random Access Memory (RAM) space, and storage capacity due to the consideration of their cost, energy consumption, and physical size. Recently, some of these systems, such as mobile phone and embedded consumer electronics, have more powerful computing capability, so they manage their data in small flash storage devices (e.g., Embedded Multi Media Card (eMMC) and Secure Digital (SD) cards) with a simple file system. However, the existing file systems usually have low space utilization for managing small files and the tail data of large files. In this work, we thus propose a dynamic tail packing scheme to enhance the space utilization of file systems over flash storage devices in embedded computing systems by dynamically aggregating/packing the tail data of (small) files together. To evaluate the benefits and overheads of the proposed scheme, we theoretically formulate analysis equations for obtaining the best settings in the dynamic tail packing scheme. Additionally, the proposed scheme was implemented in the file system of Linux operating systems to evaluate its capability. The results demonstrate that the proposed scheme could significantly improve the space utilization of existing file systems.

3D NAND has been proposed to provide a large capacity storage with low-cost consideration due to its high density memory architecture. However, 3D NAND needs to consume enormous time for garbage collection because of live-page copying overhead and long block erase time. To alleviate the impact of live-page copying on the performance of 3D NAND, a sub-block erase design has been designed. With sub-block erase design, this paper proposes a performance booster strategy to extremely boost the performance of garbage collection. As experimental results shows, the proposed strategy has a significant improvement on the average response time.

Summary The concept of green storage in cluster computing has recently attracted enormous interest among researchers. Consequently, several energy‐efficient solutions, such as multi‐speed disks and disk spin down methods, have been proposed to conserve power in storage systems and improve disk access. Some researchers have assessed their proposed solutions via simulations, while others have used real‐world experiments. Both methods have advantages and disadvantages. Simulations can more swiftly assess the benefits of energy‐efficient solutions, but various measurement errors can arise from procedural shortcomings. For instance, many power simulation tools fail to consider how heat increases the power overhead of disk operations. Some researchers claim that their modeling methods reduce the measurement error to 5% in the single disk model. However, the demand for large‐scale storage systems is growing rapidly. Traditional power measurement using a single disk model is unsuited to such systems because of their complex storage architecture and the unpredictability of numerous disks. Consequently, a number of studies have conducted real machine experiments to assess the performance of their solutions in terms of power conservation, but such experiments are time consuming. To address this problem, this study proposes an efficient simulation tool called Benchmark Analysis Software for Energy‐efficient Solution (BASE), which can accurately estimate disks' power consumption in large‐scale storage systems. We evaluate the performance of BASE on real‐world traces of Academia Sinica (Taiwan) and Florida International University. BASE incorporates an analytical method for assessing the reliability of energy‐efficient solutions. The analytical results demonstrate that the measurement error of BASE is 2.5% lower than that achieved in real‐world experiments involving energy‐estimation experiments. Moreover, the results of simulations to assess solution reliability are identical to those obtained through real‐world experiments. Copyright © 2015 Copyright © 2015 John Wiley & Sons, Ltd.

Phase-change memory (PCM) is a promising candidate as a storage medium to resolve the performance gap between main memory and storage in battery-powered mobile computing systems. However, it is more expensive than flash memory, and thus introduces a more serious storage capacity issue for low-cost solutions. This issue is further exacerbated by the fact that existing file systems are usually designed to trade space utilization for performance over block-oriented storage devices. In this work, we propose a multi-grained block management strategy to improve the space utilization of file systems over PCM-based storage systems. By utilizing the byte-addressability and fast read/write feature of PCM, a methodology is proposed to dynamically allocate multiple sizes of blocks to fit the size of each file, so as to resolve the space fragmentation issue with minimized space and management overheads. The space utilization of file systems is analyzed with consideration of block sizes. A series of experiments was conducted to evaluate the efficacy of the proposed strategy, and the results show that the proposed strategy can significantly improve the space utilization of file systems.

Recently, phase change memory (PCM) has become a promising candidate to replace dynamic RAM as main memory due to its low power consumption, fast I/O performance, and byte addressability. Accompanied with the merits, the adoption of PCM may suffer from its physical characteristic of limited write endurance. Wear leveling is a well-known approach to address this issue. For PCM main memory, the design of wear leveling should stress operation efficiency and overhead reduction. Nevertheless, conventional designs are usually dedicated to prolonging the lifetime of PCM in the best effort. In this paper, we propose a novel perspective that, instead of valuing PCM lifetime exploitation as the first priority, we turn to satisfy the product warranty period. With such a paradigm shift, the management overhead of wear-leveling mechanisms could be reduced so as to achieve further enhancement of operation efficiency. To this end, we propose a warranty-aware page management design that introduces novel criteria used to determine the state of a page by taking both the product warranty period and the write cycles of a page into consideration. Theoretical analysis is also conducted to investigate the properties and performance of the proposed management. To show the effectiveness of the proposed design, we collected real traces by running SPEC2006 benchmarks with different write intensity workloads. The experimental results showed that our design reduced the overhead to one-third that of the state-of-the-art designs while still providing the same level of performance.

Recently, many applications and users rely on cloud storage services, such as Google drive, Dropbox, iCloud and Sky drive, to store private files and system data, and cloud storage services must thus be reliable and secure. To increase reliability, previous studies have proposed a variety of erasure coding algorithms for data fault tolerance for use in storage systems. Although these data fault tolerance mechanisms increase data reliability, implementation also increases storage system costs and energy consumption due to data redundancy. However, to date energy-efficient schemes have only been developed based on a RAID architecture, and none have been implemented using an erasure coding algorithm. To address this issue, this study proposes an energy-aware I/O framework with a quality-of-service (QoS) aware data reconstruction scheduler for erasure coding algorithms, called the EEC-scheme. This approach reduces storage system energy consumption and decreases response times for user requests when the system restores failed disks. A series of experiments show that the proposed scheme can significantly reduce power consumption in storage systems.

Unlike a traditional network architecture, a software-defined networking architecture is divided into the control plane and the data plane. Network administrators use the centralized control plane to manage network authority and determine where network traffic is to be sent in the data plane. However, a centralized control structure causes a bottleneck with an overloading flow or under a DDoS attack. Under such conditions, the probability of network misconfiguration may increase rapidly and network performance may decline rapidly. This work paper proposes a hash-based mechanism that operates in the control plane to increase the reliability and scalability of the network. The hash function is utilized to assign incoming packets to queues in the control plane. The controller schedules the queues using a round-robin method to reduce the probability of failure in response to malicious attacks and to reduce transmission delay when network congestion occurs. The experimental results reveal that the proposed mechanism effectively distributes the workload and increases the reliability of the network under high-density data transmission.

The lifetime of wireless sensor networks are constrained by its limited battery capacity. Therefore, the lifetime is widely regard as a bottleneck of technique of wireless sensor network. Recently, the emerging breakthrough in wireless power transfer technique is expected to eliminate the power constraint bottleneck. In this paper, we propose an intelligent wireless charging vehicle (IWCV) strategy to resolve above problem in a dynamic and scalable approach. The IWCV strategy includes an intelligent routing strategy to traverse the sensor network topology and charging their battery to prolong their lifetime. What makes IWCV different to previous studies is that IWCV can still work even if the topology changes by re-computing the traversing route and stop time for each node in a relative short amount of time, compared with the time needed to find the shortest Hamiltoaian cycle. With the scalable and dynamic feature of IWCV, one can change their sensor network topology without down time to reconfigure the wireless charging vehicle while still maintain low energy consumption during traveling and charging in dynamic network topologies.

Summary A distributed environment requires a monitoring system to oversee the operation of various distributed nodes. A monitoring service is crucial because it ensures a high‐quality computing environment and a reliable service. The interface and framework determine the effectiveness of a monitoring system. This paper uses the concept of user‐adaptive visualization to design its interface and proposes a flexible modular framework. Designers can use the proposed modular framework to flexibly extend existing modules, design visual interfaces to satisfy user requirements, and improve system failover schemes. The implementation of such a monitoring system for monitoring data preservation nodes is also provided. The system including fault‐tolerance and notification functions supports full monitoring services for Storage Resource Broker (SRB) or integrated Rule‐Oriented Data System (iRODS) based systems. The experimental results show that the proposed framework is suitable for data preservation services and is robust and responsive when faced with system failures. Copyright © 2014 John Wiley & Sons, Ltd.

Previous studies proposed energy-efficient solutions, such as multispeed disks and disk spin-down methods, to conserve power in their respective storage systems. However, in most cases, the authors did not analyze the reliability of their solutions. According to research conducted by Google and the IDEMA standard, frequently setting the disk status to standby mode will increase the disk’s Annual Failure Rate and reduce its lifespan. To resolve the issue, we propose an evaluation function called E 3 SaRC (Economic Evaluation of Energy Saving with Reliability Constraint), which considers the cost of hardware failure when applying energy-saving schemes. We also present an adaptive write cache mechanism called CacheRAID. The mechanism tries to mitigate the random access problems that implicitly exist in RAID techniques and thereby reduce the energy consumption of RAID disks. CacheRAID also addresses the issue of system reliability by applying a control mechanism to the spin-down algorithm. Our experimental results show that the CacheRAID storage system can reduce the power consumption of the conventional software RAID 5 system by 65% to 80%. Moreover, according to the E 3 SaRC measurement, the overall saved cost of CacheRAID is the largest among the systems that we compared.

Improving the disk I/O performance is always a critical research issue in cloud computing platforms, especially for cloud computing platforms with distributed data-intensive workloads. To resolve the problem of poor disk I/O, in this paper, we propose a novel scheduling framework in the Xen-based hypervisor. In our framework, we employ a locality-aware scheduler with a deadline constraint and provide a basic QoS controller to guarantee the throughput of the cloud platform. The experimental results show that our solution increases the IOPS of Xen-based cloud platform by 9%-13% compared to the solution of early-deadline-first (EDF), deadline scheduling algorithm or Flubber. Moreover, according to the schedulability test, our solution can improve the miss deadline ratio significantly, compared to the EDF scheduling algorithm and Flubber.

Although wireless sensor devices usually have limited power, they are widely deployed in various applications, such as in remote sensing for forestry applications, military monitoring, and animal behavior. Most sensor applications deploy sensor devices in natural environments, such as forests, tunnels, and caves, to monitor targets and to collect data. To permanently monitor target environments, the battery in a sensor device needs to be recharged as its battery capacity the limited. A wireless charging vehicle uses wireless charging technology to prolong the lifetime of sensor network applications by recharging the device's battery. The wireless charging vehicle is usually equipped with a large capacity battery, an electromagnetic field, and wheels such that it can move throughout an entire sensor network to charge sensors' batteries. When the wireless charging vehicle does not need to recharge any sensor's battery, it stays at a service station to recharge its own battery. Hence, a wireless charging vehicle needs to consider two things: sensor network lifetime, and vehicle energy consumption. This work proposes a geometric solution called the Dynamic Path Generation Scheme (DPG-Scheme) to arrange the Wireless Charging Vehicle's (WCV's) travelling path while minimizing a vehicle's energy consumption and maximizing a sensor network's lifetime. The DPG-Scheme is based on the space-filling curve solution. Based on the properties of the space-filling curve, the DPG-Scheme uses space-filling curves as a space-filling curve heuristic for the NP-hard Euclidean travelling salesperson problem. The DPG-Scheme can reduce computational time when computing a wireless sensor network's (WSN's) travelling path and a new path is calculated rapidly during sensor network topology changes.

Embedded computing systems usually have limited computing power, RAM space, and storage capacity due to the consideration of their cost, energy consumption, and physical size. Some of them such as sensor nodes and embedded consumer electronics only have a small-sized flash memory as their storage with a (simple) file system to manage their data, which are usually of small sizes. However, the existing file systems usually have low space utilization on managing small files and the tail data of large files. In this work, we propose a dynamic tail packing scheme to optimize the space utilization of file systems by dynamically aggregating/packing the tail data of (small) files together. The proposed scheme was implemented in the file system of Linux operating systems to evaluate its capability. The results demonstrate that the proposed scheme could significantly improve the space utilization of existing file systems.

Flexible electronics appear in the consumer, medical, and military sectors. Thanks to the development of flexible electronics, flexible touchscreens have been widely carried on in various devices, such as mobile phones, wearable devices and hand-held tablets. Flexible touchscreens not only bring the technique of displays to next generation, but also significantly alter the interactive behaviors of users and devices. On the flexible touchscreens, when the displays are folded, some touch area around the folded line is not touchable in users' operation, and this is a critical research problem for the flexible touch screens. However, to our knowledge, little or no user interface research has solved this problem. To resolve this critical problem, in this study, we design a novel user interface, called the Auto-Adjusting Placement, which can dynamically adjust objects, such as icons, texts and pictures, on the flexible touch screens to avoid the area around the folded line and to keep the high availability/readability of the objects. Our demonstrations show that the Auto-Adjusting Placement is well performed on flexible touchscreens and therefore users have a consistent interface to use. We also filed a patent for this Auto-Adjusting Placement.

The concept of green storage in cluster computing has generated a great deal of interest among researchers in recent years. As a result, several energy-efficient solutions, such as multi-speed disks and disk spin down methods, have been proposed to conserve power in storage systems and improve disk access. Some researchers evaluate their solutions via simulations, while others utilize real-world experiments. Both methods have advantages and disadvantages. To address the problem, we propose an efficient simulation tool called BASE, which can accurately estimate the power consumption of disks in large-scale storage systems. We evaluate the performance of BASE on real-world traces from Academia Sinica (Taiwan) and Florida International University. BASE incorporates an analytical method for evaluating the reliability of energy-efficient solutions. Our analysis results show that the measurement error of BASE is 2.5% lower than that achieved in real-world experiments on energy estimation. Moreover, the results of simulations performed to evaluate a solution's reliability are the same as those derived by real-world experiments.

Virtualization is a critical technology issue in cloud computing. Virtualization technology faces two major challenges, namely, poor I/O throughput and long latency for data access. To address the issues, we present a distributed deadline modification SCAN mechanism called DDM-SCAN. We integrate the DDM-SCAN mechanism to Xen-based cloud platform. The result of our simulations show DDM-SCAN improve the I/O response time of Xen-based cloud platform 20% comparing to Flubber [1] mechanism and it also guarantee same or better quality of service (QoS) as compared with Flubber mechanism in Xen-based hypervisor. In advance, this paper provides more easy method to implement DDM-SCAN on Xen-based hypervisor rather than Flubber mechanism.

Internet of Things (IoT) has been widely researched over the past decade. Recently, many research results of IoT related to emergency system, smart building and medical system, etc. The key for IoT applications are the ability to interact with physical world through computation, communication, and machine control. However, each sensor device in IoT cannot conveniently communicate with other terminal devices through internet protocol. So, it is necessary to establish protocol translation stack or equipment between two WSN groups. That is very inefficient and high overhead cost of network construction. The development of micro-IP (uIP) solves this problem. The uIP reduce cost of protocol translation and it also realizes the machine to machine (M2M) concept in wireless sensor network. Therefore, this paper proposes a solution for porting uIP library to the wireless sensor network devices and presents the integration of a speaker module and IPv6 ready sensor device. We also propose a safe building application based on the integrated system to help people escaping from disaster environment. In conclusion, our contributions are building an IPv6 ready wireless sensor network environment and develop a safe building system to make the concept of IoT in IPv6 network environment come true.