Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

Chen-Hsiung Liu

dblp:35/8970 · DBLP profile ↗
← Back
5ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 3Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Memory systems · 40% GPUs and heterogeneous computing · 37% Parallel and multicore computing · 23%
Network and information security
3 papers
Network security · 100%
Theoretical computer science
1 paper
Algorithms and data structures · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Network security › intrusion detection and prevention
intrusion detection
0.532017
Perfect Hashing Based Parallel Algorithms for Multiple String Matching on Graphic Processing Units · IEEE Trans. Parallel Distributed Syst. 2017
Memory-efficient pattern matching architectures using perfect hashing on graphic processing units · INFOCOM 2012
Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs · IEEE Trans. Computers 2013
Network security › intrusion detection and prevention › intrusion detection
pattern matching
0.422017
Perfect Hashing Based Parallel Algorithms for Multiple String Matching on Graphic Processing Units · IEEE Trans. Parallel Distributed Syst. 2017
Memory-efficient pattern matching architectures using perfect hashing on graphic processing units · INFOCOM 2012
Memory systems
memory architecture
0.422017
Perfect Hashing Based Parallel Algorithms for Multiple String Matching on Graphic Processing Units · IEEE Trans. Parallel Distributed Syst. 2017
Memory-efficient pattern matching architectures using perfect hashing on graphic processing units · INFOCOM 2012
GPUs and heterogeneous computing
GPU computing
0.432017
Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs · IEEE Trans. Computers 2013
Memory-efficient pattern matching architectures using perfect hashing on graphic processing units · INFOCOM 2012
Perfect Hashing Based Parallel Algorithms for Multiple String Matching on Graphic Processing Units · IEEE Trans. Parallel Distributed Syst. 2017
Parallel and multicore computing › parallel algorithms › parallel string algorithms
parallel string matching
0.322017
Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs · IEEE Trans. Computers 2013
Perfect Hashing Based Parallel Algorithms for Multiple String Matching on Graphic Processing Units · IEEE Trans. Parallel Distributed Syst. 2017
Algorithms and data structures › sequence algorithms › string algorithms › string matching
aho-corasick algorithm
0.212013
Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs · IEEE Trans. Computers 2013
Algorithms and data structures › sequence algorithms › string algorithms
string matching
0.212013
Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs · IEEE Trans. Computers 2013
Network security › intrusion detection and prevention › intrusion detection
intrusion detection system
0.012012
Memory-efficient pattern matching architectures using perfect hashing on graphic processing units · INFOCOM 2012

Methods — techniques the papers use, named apart from their topics

perfect hashing · 0.9state machine parallelization · 0.5shared memory optimization · 0.5memory coalescing · 0.5GPU implementation · 0.3parallel algorithms · 0.3parallel algorithm · 0.3
YearPublicationVenuePosition
2017 Perfect Hashing Based Parallel Algorithms for Multiple String Matching on Graphic Processing Units
abstract
Multiple string matching has a wide range of applications such as network intrusion detection systems, spam filters, information retrieval systems, and bioinformatics. To accelerate multiple string matching, many hardware approaches are proposed to accelerate string matching. Among the hardware approaches, memory architectures have been widely adopted because of their flexibility and scalability. A conventional memory architecture compiles multiple string patterns into a state machine and performs string matching by traversing the corresponding state transition table. Due to the ever-increasing number of attack patterns, the memory used for storing the state transition table increased tremendously. Therefore, memory reduction has become a crucial issue in optimizing memory architectures. In this paper, we propose two parallel string matching algorithms which adopt perfect hashing to compact a state transition table. Different from most state-of-the-art approaches implemented on specific hardware such as TCAM, FPGA, or ASIC, our proposed approaches are easily implemented on commodity DRAM and extremely suitable to be implemented on GPUs. The proposed algorithms reduce up to 99.5 percent memory requirements for storing the state transition table compared to the traditional two-dimensional memory architecture. By studying existing approaches, our results obtain significant improvements in memory efficiency.
Jin-Cheng Li, Chen-Hsiung Liu, Shih-Chieh Chang 0001
IEEE Trans. Parallel Distributed Syst.3
2013 Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs
abstract
Graphics processing units (GPUs) have attracted a lot of attention due to their cost-effective and enormous power for massive data parallel computing. In this paper, we propose a novel parallel algorithm for exact pattern matching on GPUs. A traditional exact pattern matching algorithm matches multiple patterns simultaneously by traversing a special state machine called an Aho-Corasick machine. Considering the particular parallel architecture of GPUs, in this paper, we first propose an efficient state machine on which we perform very efficient parallel algorithms. Also, several techniques are introduced to do optimization on GPUs, including reducing global memory transactions of input buffer, reducing latency of transition table lookup, eliminating output table accesses, avoiding bank-conflict of shared memory, coalescing writes to global memory, and enhancing data transmission via peripheral component interconnect express. We evaluate the performance of the proposed algorithm using attack patterns from Snort V2.8 and input streams from DEFCON. The experimental results show that the proposed algorithm performed on NVIDIA GPUs achieves up to 143.16-Gbps throughput, 14.74 times faster than the Aho-Corasick algorithm implemented on a 3.06-GHz quad-core CPU with the OpenMP. The library of the proposed algorithm is publically accessible through Google Code.
Chen-Hsiung Liu, Lung-Sheng Chien, Shih-Chieh Chang 0001
IEEE Trans. Computers2
2012 Memory-efficient pattern matching architectures using perfect hashing on graphic processing units
abstract
Memory architectures have been widely adopted in network intrusion detection system for inspecting malicious packets due to their flexibility and scalability. Memory architectures match input streams against thousands of attack patterns by traversing the corresponding state transition table stored in commodity memories. With the increasing number of attack patterns, reducing memory requirement has become critical for memory architectures. In this paper, we propose a novel memory architecture using perfect hashing to condense state transition tables without hash collisions. The proposed memory architecture achieves up to 99.5% improvement in memory reduction compared to the traditional two-dimensional memory architecture. We have implemented our memory architectures on graphic processing units and tested using attack patterns from Snort V2.8 and input packets form DEFCON. The experimental results show that the proposed memory architectures outperform state-of-the-art memory architectures both on performance and memory efficiency.
Chen-Hsiung Liu, Shih-Chieh Chang 0001, Wing-Kai Hon
INFOCOM2
2011 Accelerating Regular Expression Matching Using Hierarchical Parallel Machines on GPU
abstract
Due to the conciseness and flexibility, regular expressions have been widely adopted in Network Intrusion Detection Systems to represent network attack patterns. However, the expressive power of regular expressions accompanies the intensive computation and memory consumption which leads to severe performance degradation. Recently, graphics processing units have been adopted to accelerate exact string pattern due to their cost-effective and enormous power for massive data parallel computing. Nevertheless, so far as the authors are aware, no previous work can deal with several complex regular expressions which have been commonly used in current NIDSs and been proven to have the problem of state explosion. In order to accelerate regular expression matching and resolve the problem of state explosion, we propose a GPU-based approach which applies hierarchical parallel machines to fast recognize suspicious packets which have regular expression patterns. The experimental results show that the proposed machine achieves up to 117 Gbps and 81 Gbps in processing simple and complex regular expressions, respectively. The experimental results demonstrate that the proposed parallel approach not only resolves the problem of state explosion, but also achieves much more acceleration on both simple and complex regular expressions than other GPU approaches.
Chen-Hsiung Liu, Shih-Chieh Chang 0001
GLOBECOM2
2010 Accelerating String Matching Using Multi-Threaded Algorithm on GPU
abstract
Network Intrusion Detection System has been widely used to protect computer systems from network attacks. Due to the ever-increasing number of attacks and network complexity, traditional software approaches on uni-processors have become inadequate for the current high-speed network. In this paper, we propose a novel parallel algorithm to speedup string matching performed on GPUs. We also innovate new state machine for string matching, the state machine of which is more suitable to be performed on GPU. We have also described several speedup techniques considering special architecture properties of GPU. The experimental results demonstrate the new algorithm on GPUs achieves up to 4,000 times speedup compared to the AC algorithm on CPU. Compared to other GPU approaches, the new algorithm achieves 3 times faster with significant improvement on memory efficiency. Furthermore, because the new Algorithm reduces the complexity of the Aho-Corasick algorithm, the new algorithm also improves on memory requirements.
Sheng-Yu Tsai, Chen-Hsiung Liu, Shih-Chieh Chang 0001, Jyuo-Min Shyu
GLOBECOM3