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Chris Yen

dblp:35/942 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 57% Memory systems · 38% Embedded and real-time systems · 6%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache		 0.112005
The TM3270 Media-Processor · MICRO 2005
Memory systems › cache › prefetching
data prefetching		 0.112005
The TM3270 Media-Processor · MICRO 2005
Processor architecture and microarchitecture
instruction set architecture		 0.112005
The TM3270 Media-Processor · MICRO 2005
Processor architecture and microarchitecture › special-purpose processor › application-specific processor design
media processor		 0.112005
The TM3270 Media-Processor · MICRO 2005
Processor architecture and microarchitecture › instruction-level parallelism
VLIW		 0.112005
The TM3270 Media-Processor · MICRO 2005
Embedded and real-time systems
embedded processor		 0.012005
The TM3270 Media-Processor · MICRO 2005
YearPublicationVenuePosition
2005 The TM3270 Media-Processor
abstract
We present the TM3270 media-processor, the latest TriMedia VLIW processor, tuned to address the performance demands of standard definition video processing, combined with embedded processor requirements for the consumer market. We discuss the architecture, implementation, and its first realization in a 90 nm process technology. The processor incorporates instruction set architectural (ISA) extensions and a load/store unit optimized for the video-processing domain. The ISA extensions improve the performance on video processing kernels. The data cache policies and prefetching techniques allow for efficient access to multimedia data. Finally, power consumption and performance data are presented
Jan-Willem van de Waerdt, Stamatis Vassiliadis, Sanjeev Das, Sebastian Mirolo, Chris Yen, Bill Zhong, Carlos Basto, Jean-Paul van Itegem, Dinesh Amirtharaj, Kulbhushan Kalra, Hans Van Antwerpen
 MICRO5