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Zhaolan Huang

dblp:350/0478 · DBLP profile ↗
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2ranked-venue papers
2as first author
2since 2021 · last 2025
0000-0002-8018-7092ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Embedded and real-time systems · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › efficient inference
memory-efficient inference
0.912025
msf-CNN: Patch-based Multi-Stage Fusion with Convolutional Neural Networks for TinyML · NeurIPS 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.912025
msf-CNN: Patch-based Multi-Stage Fusion with Convolutional Neural Networks for TinyML · NeurIPS 2025
Embedded and real-time systems › embedded machine learning
TinyML
0.912025
msf-CNN: Patch-based Multi-Stage Fusion with Convolutional Neural Networks for TinyML · NeurIPS 2025

Methods — techniques the papers use, named apart from their topics

directed acyclic graph · 0.9convolutional neural network · 0.9
YearPublicationVenuePosition
2025 msf-CNN: Patch-based Multi-Stage Fusion with Convolutional Neural Networks for TinyML
abstract
AI spans from large language models to tiny models running on microcontrollers (MCUs). Extremely memory-efficient model architectures are decisive to fit within an MCU's tiny memory budget e.g., 128kB of RAM. However, inference latency must remain small to fit real-time constraints. An approach to tackle this is *patch-based fusion*, which aims to optimize data flows across neural network layers. In this paper, we introduce *msf-CNN*, a novel technique that efficiently finds optimal fusion settings for convolutional neural networks (CNNs) by walking through the fusion solution space represented as a directed acyclic graph. Compared to previous work on CNN fusion for MCUs, msf-CNN identifies a wider set of solutions. We published an implementation of msf-CNN running on various microcontrollers (ARM Cortex-M, RISC-V, ESP32). We show that msf-CNN can achieve inference using 50% less RAM compared to the prior art (MCUNetV2 and StreamNet). We thus demonstrate how msf-CNN offers additional flexibility for system designers.
Zhaolan Huang, Emmanuel Baccelli
NeurIPS1
2023 U-TOE: Universal TinyML On-Board Evaluation Toolkit for Low-Power IoT
abstract
Results from the TinyML community demonstrate that, it is possible to execute machine learning models directly on the terminals themselves, even if these are small microcontroller-based devices. However, to date, practitioners in the domain lack convenient all-in-one toolkits to help them evaluate the feasibility of executing arbitrary models on arbitrary low-power IoT hardware. To this effect, we present in this paper U-TOE, a universal toolkit we designed to facilitate the task of IoT designers and researchers, by combining functionalities from a low-power embedded OS, a generic model transpiler and compiler, an integrated performance measurement module, and an open-access remote IoT testbed. We provide an open source implementation of U-TOE and we demonstrate its use to experimentally evaluate the performance of various models, on a wide variety of low-power IoT boards, based on popular microcontroller architectures. U-TOE allows easily reproducible and customizable comparative evaluation experiments on a wide variety of IoT hardware all-at-once. The availability of a toolkit such as U-TOE is desirable to accelerate research combining Artificial Intelligence and IoT towards fully exploiting the potential of edge computing.
Zhaolan Huang, Koen Zandberg, Kaspar Schleiser, Emmanuel Baccelli
PEMWN1