This brief presents a cross-temperature continuous tracking system for minimum voltage point (CTC-MVPT) based on a universal delay chain (UDC) with multiple monitoring points. By leveraging the timing information provided by the timing margin indicator and timing error indicator, the CTC-MVPT system enables continuous cross-temperature tracking of the minimum voltage point (MVP), significantly reducing power. Meanwhile, the two-step adjustment technique greatly shortens the time required for voltage regulation. In addition, this work further optimizes the 0-to-1 and 1-to-0 transition deviations of the UDC. Measurement results in a 22-nm technology show that the proposed CTC-MVPT system achieves up to 17.7% power reduction over the traditional adaptive voltage scaling (AVS) system as the temperature increases from$0~^{\circ }$C to$80~^{\circ }$C. Therefore, it takes only 1.17ms to adjust the voltage from 0.55 to 0.41 V, representing a 47.8% reduction compared to the traditional scheme. Under the TT corner, the maximum deviation rate of the UDC is only 1.5%, and the maximum deviation between 0-to-1 and 1-to-0 transitions is merely 1.2%. Meanwhile, the system achieves a power gain of up to 55.3% with only a 0.26% area overhead for timing monitoring.

This brief presents a low-power 9T static random access memory (SRAM) with enhanced read sensing margin and read performance. The read decoupled port of the proposed 9T SRAM cell achieves the enhanced sensing margin by mitigating the read bitline (RBL) leakage and improves the read performance through using one-transistor read path. The multithreshold voltage devices are used in SRAM cell for improving the leakage power and performance of SRAM. Additionally, an interleaved write wordline (WWL) structure is implemented to address the write half-select issue. The measurement results of the test chip fabricated in the 22-nm FDSOI technology demonstrate that the designed 9T SRAM achieves a minimum operation voltage of 0.31 V at 1.05 MHz and can operate at 60.5 MHz when the supply voltage is 0.5 V. The minimum active energy of 18.56 fJ/access-bit is obtained at 0.33 V. Furthermore, the designed SRAM exhibits a minimum leakage power of 0.11 pW/bitcell in the retention mode.

This paper presents a low quiescent current, transient-enhanced DC-DC buck converter with an overshoot and undershoot suppression scheme, designed to support low-power SoCs. To decrease undershoot or overshoot voltage during rapid load current transitions, an overshoot and undershoot voltage detection and response scheme is proposed. The buck converter employs an adaptive constant on time control mode, and to achieve automatic transition between PWM and PFM modes, a sub-threshold zero current detector(ZCD) is introduced. To reduce quiescent current and improve efficiency under light loads, a sampling-based low-power voltage reference circuit is proposed. Implemented with a 55 nm CMOS process, the buck converter operates with a load current range of 10 μA-10 mA. It achieves a quiescent current of 230 nA and a peak efficiency of 93.2%. During a 10 mA load variation, the converter exhibits an undershoot of 36 mV and an overshoot of 34 mV.

Error detection and correction (EDC) techniques are conventionally employed in dynamic voltage and frequency scaling (DVFS) systems to eliminate timing margins preserved in ICs. However, existing error detection methods generate warning signals even when no violations occur, resulting in frequent corrections that degrade system throughput. This issue of inaccurate detection worsens with further scaling. To solve this issue, this paper presents an accuracy-oriented EDC scheme, AO-EDC. An accurate detection method, consisting of a propagation detector (PD) and an improved half-path-point insertion method, is proposed. PDs that filter out signals from other paths are inserted at the half-path points of selected paths, reducing inaccurate detection by up to 77.5%. In addition, a half-cycle clock gating circuit is proposed to reduce the redundancy of corrections. Implemented on a 22-nm process FIR circuit, post-layout simulation results demonstrate a 42.4% - 50.0% power reduction and a 106.7% - 1089.9% frequency gain at 0.9 - 0.55 V. The proposed scheme triggers fewer corrections and reduces correction timing waste, addressing the throughput degradation issue during over-scaling in DVFS systems.