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Danyal Ahsanullah

dblp:350/0970 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
0000-0002-1418-3640ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 50% Performance modeling and evaluation · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation › statistical analysis › sensitivity analysis
adjoint sensitivity analysis
0.712023
Circuit Theory of Time Domain Adjoint Sensitivity · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Electronic design automation
circuit simulation
0.712023
Circuit Theory of Time Domain Adjoint Sensitivity · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023

Methods — techniques the papers use, named apart from their topics

linearization · 0.7circuit theoretic approach · 0.7
YearPublicationVenuePosition
2023 Circuit Theory of Time Domain Adjoint Sensitivity
abstract
It was originally stated that convolution operations were required to implement adjoint sensitivity in the time domain. In this article, we revisit time-domain adjoint sensitivity with a circuit theoretic approach and an efficient solution is clearly stated in terms of device level. Key is the linearization of the energy storage elements (e.g., capacitance and inductance) and nonlinear memoryless elements (e.g., MOS, BJT DC characteristics) at each time step. Due to the finite precision of computation, numerical errors that accumulate across timesteps can arise in nonlinear elements. A methodology to suppress that error is introduced. Numerical results demonstrate that the proposed method achieves accuracy while significantly reducing computational runtime.
Danyal Ahsanullah, Zhengqi Gao, Ronald A. Rohrer
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2