Power and energy efficiency are increasingly important challenges within HPC.However, it is still important to achieve these goals while maintaining desired/high application performance.Balancing these goals involves the challenge of precise application characterization.For successful user adoption, this must avoid modifying the application and/or extraneous application profiling, and also be portable to different processors across processor generations and vendors.We propose EVeREST-C to solve these challenges.Everest targets the finer-grained individual application functions for exploiting power/energy saving opportunities via Dynamic Voltage Frequency Scaling (DVFS) in both the core and the uncore, without application-specific knowledge.Since Everest relies on a single standard and accurate performance event, IPS (instructions per second), for its characterization rather than on the (many) performance counters that can differ across platforms, it is portable across processors.Finally, the fine-grained approach enables Everest to additionally save power/energy for select communication (MPI) phases, where appropriate phases are chosen based on both their length and position in the application with regards to the memory/compute boundedness of surrounding user routines.We evaluate Everest using SPEC CPU 2017 and various MPI applications, on Intel and AMD platforms.We find that Everest saves on average 11% more energy for SPEC compared to the baseline and 8% more energy on MPI applications compared to a state-of-the-art solution.

Amid conflicting demands for ever-improving performance and maximizing energy savings, it is important to have a tool that automatically identifies opportunities to save power/energy at runtime without compromising performance. GPUs in particular present challenges due to (1) reduced savings available from memory bound applications, and (2) limited availability of low overhead performance counters. Thus, a successful tool must address these issues while still tackling the challenges of dynamic application characterization, versatility across processors from different vendors, and effectiveness at making the right power-performance tradeoffs for desired energy savings.

Hybrid CPUs are a response from industry to the increasingly difficult problem of power management in desktop-class processors. Hybrid CPUs comprise a big/performance core for regular tasks and a small/efficiency core primarily for background OS tasks. Although helpful in managing power, the introduction of two different kinds of cores in such a design significantly complicates the scheduling of applications across cores. It also introduces other issues such as ISA compatibility, OS compatibility, many processor SKUs/configurations and the difficulty with designing/validating two independent cores. We propose to simplify with the use of a single core that is application-aware and adjusts the core and the caches both based on observed IPC within application regions and priority across applications (regular versus background tasks). We show that this simpler design is similarly effective in managing system power and saving energy as the existing hybrid CPU s with two different kinds of cores.

Hybrid CPUs have recently launched in desktop and laptop devices with the goal of increasing core count at manageable power consumption. These CPUs contain ‘performance’ and ‘efficiency’ cores, with a dedicated scheduler to assign tasks to cores. We find that these cores are not well-suited for any specific class of applications, and the efficiency cores are often smaller versions of the performance cores. This reduces the efficacy of scheduling tasks to cores. We show that instructions per cycle (IPC) per core serves as a natural metric to divide applications into two distinct classes. We use this division to propose a ‘mountain’ core with large core structures and a lower dispatch/retire width and decreased execution units (and thus lower number of ports) for low IPC applications, and a ‘plateau’ core with small core structures and increased dispatch width and execution units for high IPC applications. These changes tailor the hybrid CPU to the applications being run, allowing us to improve in both power and performance. We find that when compared to a Goldencovelike performance core, the plateau core on average improves performance by 8%, performance per Watt by 14%, and ED2P by 25% for high IPC applications; the mountain core on average improves power by 30%, performance per Watt by 34%, and ED2P by 17% for low IPC applications.