Integrated circuits (ICs) are increasingly manufactured in untrusted facilities, raising concerns regarding intellectual property (IP) protection. Logic locking has emerged as a solution to address these concerns by corrupting a circuit’s functionality unless a correct secret key is applied. However, prior work has shown that system-level phenomena can undermine module-level locking strategies, motivating the need for system-aware logic locking configuration. In this paper, we propose DSMLock, a design space modeling algorithm that identifies favorable logic locking configurations for arbitrary ICs by simulating a small, carefully selected subset of the design space to generate system-level predictive models. DSMLock efficiently identifies promising solutions that meet arbitrary, designer-specified security goals with minimal power/area overhead. To evaluate the proposed algorithm, we perform two experiments. First, an exhaustive simulation of the considered logic locking design space for a RISC-V ALU demonstrated that our models achieved an averageR2> 0.99 across all design objectives and identified a locking configuration within 96% of the global optimum after simulating less than 3.6% of the design space. Second, when comparing DSMLock against three module-level locking approaches for a RISC-V processor and an APRSC communication interface, we evaluated two cost functions: power-focused and area-focused. Under the power-focused cost function, DSMLock achieved average power reductions of 42.4% and 6.0% for the locked modules in the RISC-V and APRSC designs, respectively. Under the area-focused cost function, DSMLock achieved average area reductions of 6.1% for the RISC-V locked modules and 3.3% for the APRSC locked modules. Moreover, of the 3 evaluated locking approaches, DSMLock was the only approach to meet all specified design objectives across both design objectives for all test cases.

TinyML models deployed on edge devices are increasingly adopted in safety/security-critical applications, making them a prime target for adversarial example (AE) attacks where inputs are modified to cause misclassifications. However, existing AE detection methods either require white-box model access, which is often unavailable in licensed black-box deployments, or rely on input pre-processing stages that add non-trivial latency and resource overhead, often exceeding what mission-critical applications can afford on their inference path. To address these challenges, we propose AdvScan, a runtime power analysis-based methodology for AE detection that operates in a black-box scenario and while inducing minimal latency. AdvS-can is based on the observation that AEs produce anomalous neuron activations, which, in turn, generate distinctive power-consumption signatures. The algorithm initially constructs a baseline distribution of power signatures from known benign inputs, then, at runtime, applies a one-sample t-test to determine whether a test input’s power signature significantly deviates from this baseline, thereby detecting AEs. We evaluated AdvScan using three adversarial example (AE) generation algorithms (Fast Gradient Sign Method (FGSM), Projected Gradient Descent (PGD), and Carlini–Wagner (C&W)) on three MLPerf Tiny benchmark models implemented on two target devices: the STM32F303RC (ARM Cortex-M4) and STM32L562RE (ARM Cortex-M33) microcontrollers. Across 318,400 total test inputs, AdvScan detects 99.984% of AEs with only 40 false negatives and zero false positives. These results demonstrate the viability of power-based AE detection for secure, accuracy-critical TinyML deployments in black-box environments.