The European Union’s efforts towards technological sovereignty in High-Performance Computing are driving research and development of RISC-V-based supercomputers. The DARE SGA1 project, in particular, aims to develop chips designed and owned by Europeans. This paper introduces the Italian contribution to DARE SGA1 regarding pathfinding activities toward future RISC-V-based accelerator designs, reliability improvements, system software, and AI and Quantum Chemistry applications.

NET4EXA aims to develop a next-generation high-performance interconnect for HPC and AI systems, addressing the increasing demands of large-scale infrastructures, such as those required for training Large Language Models. Building upon the proven BXI (Bull eXascale Interconnect) European technology used in TOP15 supercomputers, NET4EXA will deliver the new BXI release, BXIv3, a complete hardware and software interconnect solution, including switch and network interface components. The project will integrate a fully functional pilot system at TRL 8, ready for deployment into upcoming exascale and post-exascale systems from 2025 onward. Leveraging prior research from European initiatives like RED-SEA, the previous achievements of consortium partners and over 20 years of expertise from BULL, NET4EXA also lays the groundwork for the future generation of BXI, BXIv4, providing analysis and preliminary design. The project will use a hybrid development and co-design approach, combining commercial switch technology with custom IP and FPGA-based NICs. Performances of NET4EXA BXIv3 interconnect will be evaluated using a broad portfolio of benchmarks, scientific scalable applications, and AI workloads.

The APEnet project is an established initiative aimed at designing interconnection boards based on FPGAs and tailored for use in HPC clusters whose nodes are arranged in a 3D toroidal network topology. Based on a custom communication protocol and network IPs, deployments of an APEnet Network Interface Card (NIC) can be configured for different operating environments. In this work, we describe APEnetX, the latest version of network architecture in the APEnet family, developed on Alveo U200 boards which leverage the 16 nm technology devices in the Ultrascale+ line by Xilinx. APEnetX features a PCIe Gen3×16 interface driven by the Queue Direct Memory Access (QDMA) Xilinx IP and adheres to the RDMA semantics, ensuring efficient high bandwidth data transfer without the involvement of the host operating system. The communication between adjacent nodes is handled through a proprietary lightweight protocol and enabled by the high-speed serial embedded transceivers of the FPGA, while a custom full crossbar switch and an optimized router allow for the implementation of a direct torus topology. Together with a proprietary software driver, a low level communication library and a dedicated MPI library, APEnetX lines up with current application standards in HPC systems. In addition, the release of an APEnetX network simulator allows for testing network functionalities at large scale. The achievement of this work is twofold: we enhance the performance of the previous APE net cards reaching 2 µs user-level latency over the PCIe for small packet transmission between topologically adjacent host nodes; we define the requirements of the communication generated by a reference spiking neural network simulator (NEST) to drive the co-design of future APE net generation.

The TEXTAROSSA project aims to bridge the technology gaps that exascale computing systems will face in the near future in order to overcome their performance and energy efficiency challenges. This project provides solutions for improved energy efficiency and thermal control, seamless integration of heterogeneous accelerators in HPC multi-node platforms, and new arithmetic methods. Challenges are tacked through a co-design approach to heterogeneous HPC solutions, supported by the integration and extension of HW and SW IPs, programming models, and tools derived from European research.