Modern computer architectures face challenges in balancing hardware overhead and performance. Binary computing, known for its compactness, requires hardware area that scales quadratically with precision, while unary computing, despite its simplicity, suffers from exponentially increasing computation time. This paper introduces Unary Positional System (UPS), a paradigm that combines spatial and temporal characteristics to address this trade-off. We develop UPS-based architectures to perform fundamental arithmetic operations, and apply it to GEMM and superconductor FFT processor. Experimental results show that UPS bridges the gap between binary and unary computing, offering a balanced solution with flexibility for further optimization.

Spiking Neural Networks (SNNs) face increasing challenges for efficient deployment as architectures grow in complexity, necessitating network pruning to improve energy and computational efficiency. Existing pruning methods primarily focus on a single form of sparsity, overlooking the importance of joint pruning, which is critical for minimizing synaptic operations (SOPs) and enhancing energy efficiency. This paper presents a novel dynamic joint pruning framework that leverages both spatiotemporal spike sparsity and weight sparsity to minimize SOPs in SNN inference. Based on a comprehensive analysis of the SOPs model, we introduce an integrated solution that combines a multi-stage masking mechanism for fine-grained neuron firing threshold control, a temporal attention batch normalization (TABN) module with learnable time scaling factors, and a dynamic sparse strategy that adjusts importance coefficients based on real-time computational impact. Experimental results on CIFAR-10, CIFAR-100, and ImageNet validate the effectiveness of proposed framework. Our method achieves up to $126.38 \times$ compression ratio of SOPs on CIFAR-10 with minimal accuracy loss, establishing a new state-of-the-art in energy-efficient SNN pruning.

ABSTRACT Spiking neural networks (SNNs) have gained significant attention due to their energy‐efficient and multiplication‐free characteristics. Despite these advantages, deploying large‐scale SNNs on edge hardware is challenging due to limited resource availability. Network pruning offers a viable approach to compress the network scale and reduce hardware resource requirements for model deployment. However, existing SNN pruning methods cause high pruning costs and performance loss because they lack efficiency in processing the sparse spike representation of SNNs. In this paper, inspired by the critical brain hypothesis in neuroscience and the high biological plausibility of SNNs, we explore and leverage criticality to facilitate efficient pruning in deep SNNs. We first explain criticality in SNNs from the perspective of maximizing feature information entropy. Second, we propose a low‐cost metric to assess neuron criticality in feature transmission and design a pruning‐regeneration method that incorporates this criticality into the pruning process. Experimental results demonstrate that our method achieves higher performance than the current state‐of‐the‐art (SOTA) method with up to 95.26% reduction in pruning cost. The criticality‐based regeneration process efficiently selects potential structures and facilitates consistent feature representation. Our code is available at https://github.com/MmPple/pruning‐criticality .

The rapid single-flux-quantum (RSFQ) superconducting technology is highly promising due to its ultra-high-speed computation with ultra-low-power consumption, making it an ideal solution for the post-Moore era. In superconducting technology, information is encoded and processed based on pulses that resemble the neuronal pulses present in biological neural systems. This has led to a growing research focus on implementing neuromorphic processing using superconducting technology. However, current research on superconducting neuromorphic processing does not fully leverage the advantages of superconducting circuits due to incomplete neuromorphic design and approach. Although they have demonstrated the benefits of using superconducting technology for neuromorphic hardware, their designs are mostly incomplete, with only a few components validated, or based solely on simulation. This paper presents SUSHI (Superconducting neUromorphic proceSsing cHIp) to fully leverage the potential of superconducting neuromorphic processing. Based on three guiding principles and our architectural and methodological designs, we address existing challenges and enables the design of verifiable and fabricable superconducting neuromorphic chips. We fabricate and verify a chip of SUSHI using superconducting circuit technology. Successfully obtaining the correct inference results of a complete neural network on the chip, this is the first instance of neural networks being completely executed on a superconducting chip to the best of our knowledge. Our evaluation shows that using approximately 105 Josephson junctions, SUSHI achieves a peak neuromorphic processing performance of 1,355 giga-synaptic operations per second (GSOPS) and a power efficiency of 32,366 GSOPS per Watt (GSOPS/W). This power efficiency outperforms the state-of-the-art neuromorphic chips TrueNorth and Tianjic by 81 and 50 times, respectively.