In this article, we propose a method for sizing an arbitrary combinational datapath to minimize its energy consumption. Our method involves deriving expressions for the components of energy consumption at both the stage and path levels. In this work, we identify overshoot energy ($E_{\text {OS}}$) consumption as a previously unreported component contributing to energy consumption, particularly significant in the near/sub-threshold voltage regime. We determine that this$E_{\text {OS}}$consumption is proportional to the input and output transition times and size of a logic gate at a particular stage of a datapath. We also observe that, for a given number of stages (N) and path effort, the total energy consumption is optimized when the stage effort (f) in a datapath is kept constant. Based on our observations and derivations of all the energy components and the requirement for a constant “f” in the datapath, we develop a method to minimize the energies of a logic circuit while maintaining the timing closure requirement. We determine that the non-critical paths (NCPs) must be sized to a minimum “f” while maintaining the timing requirements. We verified our models on several ISCAS and EPFL benchmark circuits with an average reduction of 28.1% (41.2%) and 19.2% (28.4%) in energy consumption [figure of merit (FoM)], respectively. The proposed methodology predicts the total energy consumption at a stage and path level of N-stage logic, with only one-time SPICE simulation on a single stage, with a maximum error of 1.3% and 1.62%, respectively, against SPICE simulations. The simulations are performed in Synopsys HSPICE environment with ST Microelectronics 65 nm CMOS and 28 nm FDSOI technology nodes, resulting in a very good agreement with the developed methodology.

We propose switching activity factor-based effective current source model (SAFE) for aging-aware static timing analysis (STA), a new technique for estimating the timing performance of digital circuits. SAFE is based on the development of device-level variation-aware analytical timing models of stacked and multistage logic cells (commonly employed transistor topologies in a synthesized netlist of a random logic path), which drastically reduces the recharacterization efforts of the standard cells. The models developed are derived as a function of input transition time$(T_{R})$and load capacitance$(C_{L})$. The timing performance of a standard cell degrades with threshold voltage$(V_{\mathrm {th}})$degradation in a MOS device due to various aging mechanisms. SAFE, makes the entire STA process aging aware by updating its model coefficients with$V_{\mathrm {th}}$degradation caused by aging. It is achieved by proposing a method for estimating$V_{\mathrm {th}}$degradation under various stress conditions, including static, dynamic, and asymmetric, that applies to any process design kit (PDK). To consider asymmetric aging, we have developed a method to find effective switching activity factor$(\alpha _{\mathrm {eff}})$for N-stage stacked and N-stage parallel logic which is used to find the value of switching activity factor$(\alpha)$at intermediate nodes in pipelined logic circuits. Our simulations are performed in Mentor Graphics Eldo SPICE environment using STMicroelectronics 28 and 65-nm CMOS process. The proposed technique provides a high-simulation accuracy (2.5% average error) when compared with SPICE simulations. Finally, we achieved a ~98.14% reduction in the required number of simulations using SAFE when compared with a completely SPICE/Aging simulation-based approach.

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage$(V_{\mathrm{ th}})$of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time ($t$). A device-level approach for$V_{\mathrm{ th}}$degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of$t$. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with$t$to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.