High Bandwidth Memory (HBM) is utilized in HPC and AI/ML systems, as it provides a higher data rate and also a high memory capacity by stacking DRAM dies. In the quest for a higher HBM capacity, as the number of stacked DRAM dies is increased, the number of inter-die junctions with lower heat conductivity also goes up. This encourages the formation of localized high-temperature zones (hotspots), particularly with streaming memory accesses. With the current HBM address mapping, such accesses are directed to vertically-adjacent stack regions. To avoid data errors and thermally-induced damages from mechanical stresses, throttling mechanisms are employed to temporarily block requests to heated-up regions to let them cool off. Heating within the HBM stack is, therefore, the practical limiter of the number of layers and HBM capacity. A technique is proposed to remap streaming accesses to vertically non-adjacent physical banks in HBMs to reduce hotspots and, thus, throttling, to support more HBM layers. This mechanism is extended with activity-count based throttling to avoid per-bank temperature sensors. These mechanisms are evaluated using a cycle-level GPGPU simulator, validated device models, and a 3D heat propagation model to demonstrate their advantages.

Heterogeneous integration has enabled the interconnection of chiplets in 2.5D and 3D configurations within a package. Stacking a high-performance multi-core processor chip let on top of another is challenging due to hot spot exacerbation in the stack. Temperature-induced DVFS throttling defeats any potential performance gain that results from the shorter vertical connections in-between the on-chip interconnection networks in each chip let. We present and evaluate minimally-invasive floor-plan transformation techniques that space out chiplet hot spots away from each other in the 3D stack using layout mirroring and offsetting. Chiplet redesign efforts are reduced, and cycle times are preserved. The resulting thermally-aware multi-core chiplet stacking techniques reduce the peak temperatures and temperature-induced performance throttling compared to naive chiplet stacking. Empty offset areas are then used to extend the on-chip cache capacity for further performance improvement. The multi-core stacking techniques are illustrated on a 14 nm Intel Skylake-SP-like (server) floorplan model using a cycle-level multi-core CPU performance simulator incorporating power and thermal modeling components.

Control flow attacks exploit software vulnerabilities to divert the flow of control into unintended paths to ultimately execute attack code. This paper explores the use of instruction and data tagging as a general means of thwarting such control flow attacks, including attacks that rely on violating pointer integrity. Using specific types of narrow-width data tags along with narrow-width instruction tags embedded within the binary facilitates the security policies required to protect against such attacks, leading to a practically viable solution. Co-locating instruction tags close to their corresponding instructions within cache lines eliminates the need for separate mechanisms for instruction tag accesses. Information gleaned from the analysis phase of a compiler is augmented and used to generate the instruction and data tags. A full-stack implementation that consists of a modified LLVM compiler, modified Linux OS support for tags and a FPGA-implemented CPU hardware prototype for enforcing CFI, data pointer and code pointer integrity is demonstrated. With a modest hardware enhancement, the execution time of benchmark applications on the prototype system is shown to be limited to low, single-digit percentages of a baseline system without tagging.