Two-step linear-exponential architectures can be applied to incremental ADCs (IADC) to achieve high resolution. In the first step, the ADC works as a normal first-order IADC while, in the second step, the exponential integrator is used to implement extended counting. There exist two architectures for the implementation of the exponential step, where the only difference depends on whether the input signal is connected or disconnected. By conducting a comparative analysis on such two slightly different linear-exponential architectures, we propose to combine the exponential and slope techniques to further boost the resolution without degrading its original thermal-noise suppression ability and DWA effectiveness. Mathematical analysis and simulation results are presented to confirm the principle of the proposed IADC.

This paper presents a two-phase linear-exponential incremental analog-to-digital converter (IADC) with using second-order noise coupling (NC). In the first phase, it works as a first-order IADC. Then the second-order NC path is activated in the second phase to significantly expedite the accumulation speed. Moreover, during the second phase, the integrator is disabled to achieve a large maximum stable amplitude (MSA). Simulations demonstrated that the proposed architecture could achieve a higher signal-to-quantization-noise ratio (SQNR) while avoiding the noise penalty and keeping the high effectiveness of data weighting averaging (DWA) compared with the prior art with using first-order NC. Mathematical analysis and further simulation results are presented to confirm the theory of the proposed structure.