Capacitive sensor array (CSA) is vital in precise monitoring for lab-on-chip (LOC) systems. However, shrinking electrode sizes to increase spatial resolution bring challenges like noise interference and large data volumes. This paper presents an FPGA-based system that addresses these problems with multiple sampling (MS) and pixel-wise accumulation (PWA). MS reduces Gaussian noise by sampling multiple frames and retaining only representative data points, while PWA compresses data using Block RAM and minimal combinational logic, reducing size from 118 Mb to 0.46 Mb and boosting SNR to 25.30 dB. The system enables real-time monitoring every 5 seconds instead of 17 minutes, with pipeline sensing and transmission further optimizing sensing time. Experiments demonstrate its effectiveness in distinguish between droplets and monitor evaporation in real time. MS and PWA can be easily integrated into future chip designs, offering scalable solutions for fast and precise monitoring in LOC environments.

Single-photon avalanche diodes (SPADs) have attracted a lot of attention these days because of the ability to detect a single photon for many emerging applications. However, planar SPAD sensor arrays often suffer from serious photon loss because the readout bottleneck dominates the overall dead time. This paper presents a stack-based in-pixel storage circuit for high-throughput SPAD imaging. The proposed circuit helps a SPAD imaging chip solve the buffer saturation problem and reduces its dead time by half compared to single-bit storage. Fabricated in TSMC HV$0.18\ \mu \mathrm{m}$CMOS technology, each pixel in the SPAD array can record at most three photons in 50 ns, resulting in 40Mfps. The minimum integration time to form an 8-bit image is reduced to$6.4\ \mu \mathrm{s}$while maintaining global shutter exposure.

Single-photon avalanche diode (SPAD) imagers have recently emerged in the fields of high-resolution imaging, such as fluorescence lifetime imaging microscopy. This paper presents a new design of passive quenching active reset (PQAR) circuit for high timing-resolution SPAD imagers. The PQAR circuit contains a logic control circuit for self-restoring and dead time reduction in the event of two adjacent incoming photons. Post-layout simulation result shows that the dead time of the sensor has been reduced to 5.46 ns for two adjacent incoming photons, and measurement result shows that the jitter of the photon-induced signal width has been reduced to 63ps. We also present the properties and measurement results of the passive quenching passive reset circuit and the passive quenching active clock-driven reset circuit. Comparison shows that of the three circuits we demonstrate, the PQAR circuit is better suited for the high timing-resolution SPAD imagers.