Achieving efficient and effective automation in hierarchical analog/mixed-signal (AMS) integrated circuit layout synthesis remains a significant challenge in the electronic design automation domain, due to the vast design space and diverse layout requirements. The state-of-the-art AMS layout automation tools, like ALIGN and MAGICAL-EDA, utilize constraints extracted by designers to address this challenge. This constraint extraction is, however, a problem on its own when the number of constraints gets larger and the designs become more complicated. Recently, graph neural network (GNN)-based methods have been explored to extract inter-symmetry constraints in analog circuits, although with limited accuracy and applicability for other constraint types on hierarchical AMS circuits. In this article, we propose a generalized constraint learning and transfer (CLT) framework that can address a generalized, wider range of constraints and offers a more accurate and robust CLT methodology for hierarchical AMS circuit layout synthesis. A generate-and-aggregate approach enhanced by net-first GNN (Nest-GNN) and selective topological search (SelecTS) algorithms is introduced to accurately and efficiently learn and transfer to a more generalized range of constraint, including symmetry, impedance matching, and grouping for both placement and routing (P&R). This framework is the first one, to the best of our knowledge, to transfer constraint types such as grouping and impedance matching, for P&R on hierarchical AMS circuits. Tested on hierarchical AMS circuits with up to 25 hierarchies, over 1,000 devices, and more than 500 nets, our framework achieves an average CLT F1 score of over 0.98 for all constraint types in an efficient way, outperforming the state-of-the-art CLT methods.

Analog/mixed-signal circuits are key for interfacing electronics with the physical world. Their design, however, remains a largely handcrafted process, resulting in long and error-prone design cycles. While the recent rise of AI-based reinforcement learning and generative AI has created new techniques to automate this task, the need for many time-consuming simulations is a critical bottleneck hindering the overall efficiency. Furthermore, the lack of explainability of the resulting design solutions hampers widespread adoption of the tools. To address these issues, a novel agentic AI framework for sample-efficient and explainable analog circuit sizing is presented. It employs a multi-agent workflow where specialized Large Language Model (LLM)-based agents collaborate to interpret the circuit topology, to understand the design goals, and to iteratively refine the circuit’s design parameters towards the target goals with human-interpretable reasoning. The adaptive simulation strategy creates an intelligent control that yields a high sample efficiency. The AnaFlow framework is demonstrated for two circuits of varying complexity and is able to complete the sizing task fully automatically, differently from pure Bayesian optimization and reinforcement learning approaches. The system learns from its optimization history to avoid past mistakes and to accelerate convergence. The inherent explainability makes this a powerful tool for analog design space exploration and a new paradigm in analog EDA, where AI agents serve as transparent design assistants.

Truly full automation of analog/mixed-signal (AMS) integrated circuit design and layout has long been a target in electronic design automation. Making good use of human designer heuristics as constraints that steer today's tools is key to balancing efficiency and design space exploration. However, explicitly getting the constraints for every circuit from designers is the weak spot. Learning-based methods on the other hand can learn efficiently from training examples. This paper proposes a flexible framework that can self-learn various layout constraints for a circuit from some expert-generated example layouts. Constraints like alignment, symmetry, and device matching are learned from those expert layouts with the generate-and-aggregate methodology. Secondly, through feature matching, the learned knowledge can then be transferred as constraints for the layout synthesis of different circuit topologies, making the approach flexible and technology-agnostic. Experimental results show that our framework can learn constraints with 100% accuracy. Compared to other state-of-the-art tools, our framework also achieves a high efficiency and a high transfer accuracy over various types of constraints.

This work presents a chemical readout system designed in TSMC 180 nm technology. The proposed design has an input range of 0-1.8 V, linearity (R2) of over 0.997, high sensitivity of 600 KHz/pH, a maximum frame rate of 1.4 μ$s$and a small chip area. The readout system includes an Ion-Sensitive Field Effect Transistor (ISFET) front-end that works in the saturation region, trans-linear circuits for linearity enhancement, and a CCO (Current Controlled Oscillator)-based ADC as an analogue to digital converter. This system was designed to provide a good balance between input range, linearity, and silicon area. The proposed architecture is capable of compensating for 400 mV of trapped charge by changing the biasing current of the lineariser as a universal quadratic equation solver.