Ashfakh Huluvallay

dblp:352/9047 · DBLP profile ↗
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4ranked-venue papers
1as first author
4since 2021 · last 2026
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-author · 4 since 2021
YearPublicationVenuePosition
2026 Low Supply, Impedance-Boosted Current Mirror Using Back-Gate in FD-SOI Technology
Roopesh G. L, Arpan Jain, Soham Bhattacharyya, Ashfakh Huluvallay, Andleeb Zahra, Zia Abbas
ISCAS4
2026 A 0.5V 72-pW Process and Temperature Compensated Voltage Reference
Vikkram Srinivasan, Damini Chandi Priya A, Ashfakh Huluvallay, Arpan Jain, Abhishek Pullela, Andleeb Zahra, Zia Abbas
ISCAS3
2025 Low-Power Voltage Reference: Review & Progress
abstract
This paper explores advanced voltage reference designs with extremely low power consumption, specifically under one microwatt. These designs are crucial for portable electronic systems that rely on minimal power. The paper categorizes these voltage references based on the types of devices used to generate temperature-proportional or complementary signals. It also provides key design examples to illustrate these concepts. Additionally, the paper enhances understanding by conducting a comparative analysis of performance metrics, including power consumption, temperature coefficient, physical size, and resistance to variations in the manufacturing process.
Abhishek Pullela, Ashfakh Huluvallay, Arpan Jain, Zia Abbas, Inhee Lee 0001
VTS2
2023 A 7 nW, 1 kHz, -40-170°C Relaxation Oscillator with Switch-Leakage Compensation for Low-Power High-Temperature IoT Systems
abstract
This paper proposes a low-power relaxation oscillator for low-power high-temperature IoT systems. It generates a 959 Hz clock signal from −40 to 170°C, consuming 6.75 nW at 0.65 V. A proposed switch-leakage compensation scheme nullifies the effects of body diode and subthreshold leakages on oscillator output frequency at high temperatures, thereby obtaining a wide operating temperature range. The oscillator implemented in a 180 nm CMOS process achieves a temperature coefficient of 40 ppm/°C from −40 to 170 °C at 0.65 V and a line sensitivity of 0.5 %/V from 0.65 to 2.4 V at room temperature, in simulation. Compared with state-of-the-art sub-$\mu\mathrm{W}$oscillators, this circuit obtains the highest operating temperature and the maximum temperature range.
Ashfakh Huluvallay, Abhishek Pullela, Ehab A. Hamed, Arpan Jain, Naveen Dasari, Zia Abbas, Inhee Lee 0001
ISCAS1