Resistive random-access memory (RRAM) based compute-in-memory (CIM) is an emerging approach to address the demand for practical implementation of artificial intelligence (AI) on resource constrained edge devices by reducing the power-hungry data transfer between memory and processing unit. However, the state-of-the-art RRAM CIM designs fail to strike a balance between precision, energy efficiency, throughput, and latency. This work merges the techniques of CIM and compute-near-memory (CNM) to deliver high precision, high energy efficiency, high throughput, and low latency. In this paper, a 256Kb RRAM based CNM macro fabricated in TSMC 40 nm process is presented featuring: 1) opposite weight mapping with variation-robust SA to mitigate the impact of RRAM device variations on MAC (Multiply-Accumulate) results; 2) switched-capacitor-based analog multiplication circuit to achieve highly parallel computing of 128 4-bit by 4-bit MAC result with low power consumption and high operation speed; and 3) joint optimization of hardware and software to compensate for the accuracy loss after considering the non-idealities of circuits. The macro achieves a low latency of 17ns and high energy efficiency of 71 TOPS/W for MAC operations with 4-bit input, 4-bit weight and 4-bit output precision. It is used to accelerate the convolution process in the Light-CSPDenseN et AI model, resulting in a high accuracy of 86.33% on Visual Wake Words dataset.

Computing-in-memory (CIM) is renowned in deep learning due to its high energy efficiency resulting from highly parallel computing with minimal data movement. However, current SRAM-based CIM designs suffer from long latency for loading weight or feature maps from DRAM for large AI models. Moreover, previous SRAM-based CIM architectures lack end-to-end model inference. To address these issues, this paper proposes CIMR-V, an end-to-end CIM accelerator with RISC-V that incorporates CIM layer fusion, convolution/max pooling pipeline, and weight fusion, resulting in an 85.14% reduction in latency for the keyword spotting model. Furthermore, the proposed CIM-type instructions facilitate end-to-end AI model inference and full stack flow, effectively synergizing the high energy efficiency of CIM and the high programmability of RISC-V. Implemented using TSMC 28nm technology, the proposed design achieves an energy efficiency of 3707.84 TOPS/W and 26.21 TOPS at 50 MHz.

Computing-in-memory (CIM) is popular for deep learning due to its high energy efficiency owing to massive parallelism and low data movement. However, current ReRAM based CIM designs only use partial parallelism since fully parallel CIM could suffer lower model accuracy due to severe nonideal effects. This paper proposes a robust fully-parallel ReRAM-based CIM processor for deep learning. The proposed design exploits the fully-parallel computation of a$1024\mathrm{x}1024$array to achieve 110.59 TOPS and reduces nonideal effects with in-ReRAM computing (IRC) training and hybrid digital/IRC design to minimize the accuracy loss with only 1.55%. This design is programmable with a compact CIM-oriented instruction set to support various 2-D convolution neural networks (NN) as well as hybrid digital/IRC designs. The final implementation achieves a 2740.41 TOPS/W energy efficiency at 125MHz with TSMC 40nm technology, which is superior to previous designs.