This paper presents a receiver design that has a summer integrated latch in a decision feedback equalizer (DFE) for wireline chip-to-chip communication. The proposed DFE cancels the first post-cursor by modulating the rising edge of the clock of the latch. This leads to a reduced clock-to-Q delay of the latch along with the improvement in loop delay for the first tap of the DFE. The proposed 1-tap DFE using the clock-based summer-latch (CSL) along with a single-stage continuous time linear equalizer (CTLE) has been implemented in the front end of the receiver and fabricated in TSMC 65-nm CMOS technology. The prototype has been measured at a data rate of 9 Gb/s for a FR4 channel having a loss of 14.75 dB at Nyquist frequency. The total power consumption of the implemented receiver is 3.7 mW with an energy efficiency of 0.41 pJ/b for a BER$10^{-12}$. The complete 1-tap quarter rate DFE occupies an core area of 0.00525 mm2.

This paper presents a full-duplex simultaneous bidirectional (FD-SBD) signaling transceiver designed to overcome the switching supply noise (SSN). The signal-to-noise ratio (SNR) is impacted mainly by transmitter echo signal, inter-symbol interference (ISI), SSN, etc. This paper primarily focuses on comparing the impact of SSN on the transceiver. In general, the voltage mode (VM) transmitter injects more SSN compared to the current mode (CM) transmitter. To address this, the proposed architecture combines voltage mode source series terminated (VM-SST) and current mode logic (CML) transmitters to improve SNR by mitigating the effect of SSN. In addition, this paper proposed a passive R-Gm hybrid for linear and energy-efficient subtraction of the transmitted signal and extracting the received signal. Implemented in TSMC-65 nm CMOS technology for a link with 3 dB insertion loss at 5 GHz Nyquist frequency, the simulated results of the proposed architecture improve the eyeopening by 30% at 10+10 Gb/s SBD data rate.

This paper presents a current mode (CM) replica driverless full-duplex simultaneous bidirectional (FD-SBD) signaling transceiver for chip-to-chip interconnect. For FD-SBD signaling a hybrid architecture is used to extract the received signal from the channel by canceling the transmitted signal. However, the pin package parasitics at the interface increases the near-end reflection and increases the cancellation error which reduces the received signal eye opening. Reducing the cancellation error by using filters increases the power consumption along with the complexity. In the case of single-ended full-duplex signaling with dedicated wires for transmitting and receiving, the received signal eye opening is affected significantly by the cross-talk and power supply noise. Therefore, in this work a hybrid of differential and common mode signaling is used to reduce the cancellation error and common-mode noise to increase the data rate. The proposed transceiver does not require an additional replica driver to retrive the received signal unlike conventional transceivers. The architecture is designed using 65 nm CMOS technology for a 7.5-inch channel with 6.46 dB insertion loss at 5 GHz Nyquist frequency. An aggregate full-duplex data rate of 30 Gb/s with an energy efficiency of 0.43 pJ/b is achieved in this work.

This paper presents a single-ended voltage-mode (VM) simultaneous bidirectional (SBD) transceiver for chip-to-chip interconnects. A hybrid network in the receive path cancels the transmitted signal to extract the received signal enabling SBD signaling. The conventional source-series terminated (SST) and trans-impedance amplifier (TIA)-based transmitters used in the SBD signaling transceivers consume high power to minimize output impedance variation. The proposed design minimize this variation with low power consumption, thereby leading to a low-power transceiver. In addition, the power consumption while incorporating feed-forward equalizer (FFE) is reduced by using current-mode implementation in the proposed transceiver. Implemented using TSMC PDK in 65 nm technology, the simulation results gives an energy efficiency of 0.35 pJ/b at 20 Gb/s SBD data-rate.

This paper presents an energy-efficient full-duplex simultaneous bidirectional (FD-SBD) signaling transceiver to double the aggregate data transfer per pin for serial links. For achieving FD-SBD signaling, the transceiver employs a resistor-transconductance (R-Gm) hybrid-based subtractor to enable concurrent transmission and reception of non-return to zero (NRZ) data stream on a single differential channel. The transmitter of a conventional current-mode R-Gm hybrid transmits through a split termination, which effectively reduces the impedance at the transmitting node and increases the power consumed by the transmitter by almost two times compared to the conventional current-mode logic (CML) transmitter. In this work, we have proposed a current-sharing topology by reusing the same transmitter current in both transceivers so that the power consumed by the transmitters is reduced by$2\times $. A prototype of the proposed transceiver has been implemented in 65 nm CMOS technology for full-duplex signaling across a short FR4 link with a 2.5 dB insertion loss at Nyquist frequency. Measured results give an energy efficiency of 1.7 pJ/b at an aggregate data rate of 8.6 Gb/s with a bit error rate (BER)$\lt 10^{-12}$.

In this paper, a current mode (CM) full-duplex simultaneous bidirectional (FD-SBD) transceiver has been presented for chip-to-chip interconnect. To enable simultaneous bidirectional communication, the transceiver incorporates a hybrid network in the receive path, which not only eliminates the transmitted signal but also its reflections due to channel imperfections. A front-end programmable active delay line (PADL) and an approximate impedance matching network (IMN) at replica end forms the hybrid network to move and reduce the echo from received signal (RX) sampling point. The architecture has been implemented using 65 nm CMOS technology for a short channel with 4.375 dB insertion loss at 7.5 GHz. Post-layout simulation of the bidirectional transceiver with the link, gives an energy efficiency of 1.8 pJ/b, at aggregate data rate of 26 Gb/s.