In this paper, a rapid binary search-based calibration method for capacitor mismatch errors in CDAC structures is proposed. Limitations of existing methods, such as the need for ADC architecture modifications, long convergence times, and high design complexity, are addressed by this approach. By employing a simple binary search algorithm, capacitor weights are quickly optimized to maximize the SNDR, effectively calibrating capacitor mismatch errors. The implementation of this method is relatively straightforward, with comparatively low computational resource requirements, offering strong flexibility. Simulation results for a 14-bit Pipelined-SAR ADC model indicate that, after calibration, average SNDR and SFDR improvements of 8.74 dB and 20.65 dB, respectively, were achieved.

This paper introduces a 0.5-V, two-stage, pseudo-differential bulk-driven operational transconductance amplifier with high gain and linearity for low-power continuous-time applications. The input stage’s common-mode feedback utilizes a linear resistor detector with a conductance reduction cross-coupled pair to mitigate the loading effect of the common-mode detector resistor at ultra-low power operations. Temperature dependence of the conductance reduction circuit is compensated. The impact of the conductance reduction circuit on linearity performance is explored. The output stage employs a class-AB topology and utilizes a phase lead compensator to stabilize the OTA. Implemented in 180 nm CMOS technology, this OTA achieves a DC gain and slew rate of 68 dB and 26.1 V/$\mu $s, respectively, under a capacitive load of 10 pF. The total power consumption is$34.2~\mu $W. With unit gain feedback configuration, the measured total harmonic distortion is only 0.02% at an output amplitude of 500 mVpp. Test results validate the proposed circuit, positioning it competitively compared to state-of-the-art designs.

The performance of zero intermediate frequency (IF) receiver is usually limited by the frequency dependent I/Q mismatch, which gets worse with the increase of the signal bandwidth. Because the frequency dependent errors caused by the mixer and the baseband filters are difficult to eliminate, digital calibration methods are widely adopted. Among all the calibration methods, the algorithm based on the detection in frequency domain is able to extract the error at different frequencies which makes it suitable for foreground calibration. This paper proposed a receiver I/Q mismatch calibration method applied to wideband FDD transceivers, which can extract the error in frequency domain by transmitting customized signals through transmitters. A reasonable frequency plan is adopted to avoid the interference of TX image, nonlinearity and LO leakage and the wideband I/Q mismatch is compensated by a complex finite impulse response (FIR) filter. The proposed algorithm fully utilizes the existing hardware of the receiver, achieving a good balance between algorithm performance and hardware cost, which is validated on a FDD transceiver platform and the image rejection ratio (IRR) is improved from 33dB to at least 66dB in the whole baseband with a bandwidth of 245MHz.

In this paper, a novel foreground calibration method for wideband zero IF receiver I/Q mismatch is proposed based on frequency domain feature extraction, which is suitable for the FDD transceiver integrated with digital signal processing modules. The proposed algorithm calibrates the frequency dependent mismatch through a complex digital FIR filter, and uses the transmitter as the signal source. A frequency allocation scheme is applied to avoid the interference from the transmitter image component. Mismatch factors such as LO phase and amplitude mismatch and baseband transfer function mismatch can be calibrated together directly by this method, which eliminates the error accumulation caused by multi-level cascade calibration. Finally, a high image rejection ratio is obtained, and the image component power is stably compressed below the quantization noise power in the whole baseband.